Answered: Question 1 a. Tri-state logic is often…

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Related questions

Concept explainers

Question

Please written by computer source

Question 1 a. Tri-state logic is often used in digital design to resolve the conflict that arises when more than one output is connected. With the aid of a diagram, explain how this can be used in a digital design to share a single bus. b. Examine the following VHDL statements and draw a synthesised schematic for the corresponding design. c. Using concurrent statements only, (no process), describe a decoder in VHDL which satisfies the following conditions, and draw the High level RTL schematic for this design. 3 inputs (A, B, C) and 1 output (Z). The output is equal to 1 when either input A is equal to 1 or only input C is equal to 1. All signals are of type 'std_logic d. VHDL allows the designer to describe hardware using different language constructs. Although, these constructs might have the same, or similar, functionality, the result of the synthesis is quite different. One example is the if-else and the case constructs. Explain the difference between the if-else and the case construct with respect to simulation and synthesis. entity EXAMPLE IS PORT ( P, Q, R : IN STD_LOGIC; PQ : OUT STD_LOGIC; PQR : OUT STD_LOGIC); end EXAMPLE; architecture RTL of EXAMPLE is signal PQ_SIG: std_logic; begin PQ_SIG <= P and Q; PQR <= PQ_SIG and R; PQ <= PQ_SIG; end RTL; Question 2 a. The VHDL language can use concurrent statements as well as sequential statements. Explain the difference between these two statements. b. Verification of the final ASIC is an important stage in the ASIC design process. Latches can be difficult to test at this stage. It is, therefore, important to avoid any unnecessary latches in the synthesised design. Explain how a latch can be inferred. Give a VHDL code as an example. c. Following is the entity declaration for a simple serial in parallel out (SIPO) 8 bit shift register. Write a VHDL architecture for this entity so the data can be shifted to the left (LSB first) and right (MSB first). d. Write a VHDL description for the following digital circuit. Use a synchronous, active high reset mechanism for the system. U 4 D_FF D Q ~ Q RESET CLK SET Z A B C D E CLK RST Question 3 a. The VHDL construct generic allows the designer to parameterise the design. Explain the concept behind this construct. b. One use for sequential statements in VHDL is to describe clocked circuits. Using sequential statements, design a counter in VHDL that counts from 0 to 9. The entity definition is given below. c. Mealy and Moore machines are two types of sequential machines. There are several ways to model these machines in VHDL. One approach would be to use two processes to represent the two parts of the circuit. Briefly explain how, a behavioural model of a Mealy machine can be designed using VHDL. d. The following Mealy type state diagram describes the sequence detector mechanism. Write a VHDL description of the state machine. The entity of the state machine is given below. library IEEE; use IEEE.std_logic_1164.all; entity COUNTER is port ( CLK, RST : in std_logic; COUNT : out std_logic_vector(3 downto 0) ); end COUNTER; entity sequence_detector is port ( clk,rst : in std_logic; X : in std_logic; Z : out std_logic ); end entity; Figure 3.1 state diagram of a sequence detector Page 5 of 5 Question 4 a. Explain the term 'testbench' in relation to VHDL and where the advantages in using a 'testbench' lie. b. Write a testbench that verifies the 3-bit up-counter, which is given by its entity below. Explain what you are testing. Do not use file I/Os in your testbench. c. Explain the terms setup time, hold time and aperture time in digital design with the help of a timing diagram. d. Draw the synthesis circuit for the following VHDL design. Note: do not use optimization and state all your assumptions. entity COUNTER3 is port(clock, reset, enable: in std_logic; CNT_VAL: out std_logic_vector(2 downto 0)); end COUNTER3; Process (clk) Begin If rising_edge(clk) then Q <= Data; QB <= not Data; End if; End process;

Expert Solution

Step by step

Solved in 2 steps

SEE SOLUTION Check out a sample Q&A here

Knowledge Booster

Learn more about

Need a deep-dive on the concept behind this application? Look no further. Learn more about this topic, computer-science and related others by exploring similar questions and additional content below.

Similar questions