Q1. Figure 1 shows a differential amplifier. Assume that all transistors are identical. ẞ=180, V = 0.026 Vand V = 0.7V. a) b) Show that the d.c. bias current to the differential pairs is Iccs = 0.6 mA. Calculate the d.c. voltages at the output terminals V。1 and V02- c) Given that the input signals are v₁ = 4 sin(wt) and V₁₂ = 2sin(wt) in mV, find the a.c. voltage between V01 and V02- 5kQ 9.6kQ +12 V 6kQ Figure 1 V02 *ન્મા Iccs CCS 12 ΚΩ 6kQ V12

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The circuit shown in the following in figure has: VIN= 10 V, Vz = 7.2 V@ Iz-40 mA, Izk =2 mA, IzM= 100 mA and Zz-5 2. Determine a) Maximum output voltage. b) Minimum output voltage. c) The percentage load regulation. d) The minimum permissible load resistor value. c) The maximum permissible load resistor value. R 2211 VIS

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Q.) Figure below divider bras amplifier Circuit. Givent the model Parameter : gm = 5o mS emitter (CE) Voltage BJT hibrid- TT Shows a Common riT: 6 Kr and to %3D : 00 +Vc. RI C2 Tooks touf RL Vo ihe 200 RE TCE Vs 20 a Draw the Ac eQuivalent at low Freauency Circuit Zi and b.) Determine inPut impedance at mid FreaUincy OutPut imPedance Z0 c.) Calculafe two low Cut -oFF FreQuen Cies FLC1 and FLC2 Ci and E2 respectively Such as due to the exterda al capacitors

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Problem 2: Consider a ZCS buck converter with following parameters: Vs = 100 V, Ly = 10 µH, C, = 0.01 μF The load current ranges from 0.5 to 3 A. Determine the range of switching frequency required to regulate the output voltage at 50 V.

Q 1. Determine the output voltage of the Digital-to-Analog Converter (DAC) in Figure 1(a) and plot it in Figure 1(c). The sequence of the four digit binary codes represented by the waveforms in Figure 1(b) are applied to the inputs. A high level is a binary 1and a low level is a binary 0. The least significant binary digit is Do. Do o D₁ 0- 200 ΚΩ www D₂ 0 100 ΚΩ www 50 ΚΩ www 25 ΚΩ D3 0 M 0 -0.25 -0.50 -0.75 -1.00 -1.25 -1.50 -1.75 -2.00 -2.25 -2.50 -2.75 -3.00 -3.25 -3.50 -3.75 (a) Vout (V) R₁ 10 ΚΩ o Vout +5 V Do 0 +5 V D₁ 0 +5 V 0 +5 V 0 D₂ D3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 non (c) Figure 1 I 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ||||| (b) Binary input