Presume a memory hierarchy with a two-layer cache and the following timings to access each component (timings add up): • L1: 1 cycle • L2: 4 cycles • Memory: 15 cycles A program makes 100 memory accesses, 85% of which hit in L1, 10% of which hit in L2, and 5% of which do not hit in either cache. How many cycles will be required for this program to perform these accesses?

Presume a memory hierarchy with a two-layer cache and the following timings to access each component (timings add up): • L1: 1 cycle • L2: 4 cycles • Memory: 15 cycles A program makes 100 memory accesses, 85% of which hit in L1, 10% of which hit in L2, and 5% of which do not hit in either cache. How many cycles will be required for this program to perform these accesses?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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