Present Next State State x=0 x=1 x=0 Output x=1 yayı Y2Y1 Y2Y1 Z N 00 00 01 0 0 01 00 10 0 0 10 00 10 0 1 11 00 10 1 1 Figure P9.8

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9.8 Using D flip-flops, design a logic circuit for the finite-state machine described
by the state assigned table in Figure P9.8.
Present
Next State
Output
State
x=0
x=1
x=0
x=1
y21
Y2Y1
Y₂Y1
Z
Z
00
00
01
0
0
01
10
11
883
00
10
0
0
00
10
0
1
00
10
1
1
Figure P9.8
Transcribed Image Text:9.8 Using D flip-flops, design a logic circuit for the finite-state machine described by the state assigned table in Figure P9.8. Present Next State Output State x=0 x=1 x=0 x=1 y21 Y2Y1 Y₂Y1 Z Z 00 00 01 0 0 01 10 11 883 00 10 0 0 00 10 0 1 00 10 1 1 Figure P9.8
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