Address Write 1 Enable Data In X RAM Data Out RAM diagram 16 [15:10] [9:8] [7:5] [4:0] +2 3 to 5 Bus splitting example [15:10] 6 2 3 5 [9:8] [7:5] [4:0] 16 Bus joining example

Please do the following

a. Design a 256×8 RAM by adding minimal wiring and logic to two identical 256×4 RAM components. Label the widths (in bits/lines) of the ports Address, Data In, and Data Out for each 256×4 RAM you use and for the 256×8 RAM you implement.

b. Design a 64K×8 RAM by adding minimal wiring and logic to a single provided 32K×16 RAM. (K = “kilo” = 1024)

For each:

• Connect inputs and outputs of the larger box with those of the smaller boxes representing RAMs, possibly adding combinational logic building blocks (e.g., muxes, decoders, gates) that make the logic correct.

• For each bus that contains a multi-bit value (e.g., Address); use hatch marks and width annotations to mark how many bits are carried by that bus. You must specify the number of bits (width of bus) carried by each bus.

• When a larger bus splits into or is joined from smaller buses, you must show which bit ranges from the larger bus correspond to the width of each smaller bus, as shown in the examples below: