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Please describe what this testbench code is doing. You can use comments for each line if that is easier for you. This code is using Verilog.

Please describe what this testbench code is doing. You can use comments for each line if that is easier for you. This code is using Verilog.

Database System Concepts
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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Please describe what this testbench code is doing. You can use comments for each line if that is easier for you. This code is using Verilog.

`timescale 1ns / 1ps
 
module display_tb02();
    reg [4:0] P;
    reg [1:0] X;
    wire [3:0] an;
    wire [0:7] led;
 
Disp_tester uut(
.P(P),
.X(X),
.an(an),
.led(led)
);
 
    initial 
    begin
    $display("\nTestbench start");
        {P,X}=0;    //quantity formed by concatenating....initialized to 0
   #100;
end
 
    always 
    begin
        #10; //wait for 10 * 1ns = 10ns
        if ({P,X} === 'b1111111) 
        begin
            #10;
            $display("Testbench end");
            $finish;
 
        end
 
        else 
        begin
            {P,X} = {P,X} + 1;
 
            $display("P,X=%0d,%0d",P,X); 
            $display("an,led=,%b,%b",an,led);
        end
    end   
endmodule

 

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