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P2) Draw the schematic of the CMOS logic gate that implements the function Y = A + BC. (a) Identify the input conditions for the worst case rise/fall times and the best case rise/fall times. (b) Size your transistors, such that for the worst case the gate achieves the same rise and fall times of the unit-sized inverter of P1 when your gate is driving a load capacitance of 1.5pF. (c) Using the equivalent resistance to model the transistors and neglecting the diffusion capacitances, estimate the worst case rise and fall time of your gate and compare them to that of the unit-sized inverter in P1. (d) Using the equivalent resistance to model the transistors and neglecting the diffusion capacitances, estimate the best case rise and fall time of your gate.

P2) Draw the schematic of the CMOS logic gate that implements the function Y = A + BC. (a) Identify the input conditions for the worst case rise/fall times and the best case rise/fall times. (b) Size your transistors, such that for the worst case the gate achieves the same rise and fall times of the unit-sized inverter of P1 when your gate is driving a load capacitance of 1.5pF. (c) Using the equivalent resistance to model the transistors and neglecting the diffusion capacitances, estimate the worst case rise and fall time of your gate and compare them to that of the unit-sized inverter in P1. (d) Using the equivalent resistance to model the transistors and neglecting the diffusion capacitances, estimate the best case rise and fall time of your gate.

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...
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P2) Draw the schematic of the CMOS logic gate that implements the function Y = A + BC. (a) Identify the input conditions for the worst case rise/fall times and the best case rise/fall times. (b) Size your transistors, such that for the worst case the gate achieves the same rise and fall times of the unit-sized inverter of P1 when your gate is driving a load capacitance of 1.5pF. (c) Using the equivalent resistance to model the transistors and neglecting the diffusion capacitances, estimate the worst case rise and fall time of your gate and compare them to that of the unit-sized inverter in P1. (d) Using the equivalent resistance to model the transistors and neglecting the diffusion capacitances, estimate the best case rise and fall time of your gate.
Transcribed Image Text:P2) Draw the schematic of the CMOS logic gate that implements the function Y = A + BC. (a) Identify the input conditions for the worst case rise/fall times and the best case rise/fall times. (b) Size your transistors, such that for the worst case the gate achieves the same rise and fall times of the unit-sized inverter of P1 when your gate is driving a load capacitance of 1.5pF. (c) Using the equivalent resistance to model the transistors and neglecting the diffusion capacitances, estimate the worst case rise and fall time of your gate and compare them to that of the unit-sized inverter in P1. (d) Using the equivalent resistance to model the transistors and neglecting the diffusion capacitances, estimate the best case rise and fall time of your gate.
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