Ordinarily client programs are kept from dealing with I/0 straight by I/0 guidelines in them. For CPUS having express I/0 guidelines, such I/0 assurance is guaranteed by having the I/O directions favoured. In a CPU with memory planned I/0, there is no express I/0 guidance. Which one of coming up next is valid for a CPU with memory planned I/0? (a) 1/O insurance is guaranteed by operating system routine(s) (b) 1/O insurance is guaranteed by an equipment trap (c) I/O insurance is guaranteed during framework arrangement (d) 1/O insurance is unimaginable

Ordinarily client programs are kept from dealing with I/0 straight by I/0 guidelines in them. For CPUS having express I/0 guidelines, such I/0 assurance is guaranteed by having the I/O directions favoured. In a CPU with memory planned I/0, there is no express I/0 guidance. Which one of coming up next is valid for a CPU with memory planned I/0? (a) 1/O insurance is guaranteed by operating system routine(s) (b) 1/O insurance is guaranteed by an equipment trap (c) I/O insurance is guaranteed during framework arrangement (d) 1/O insurance is unimaginable

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Assume that an interrupt mechanism uses the hardware stack to store PC and other registers of the interrupted computations. The interrupt mechanism recognizes 4 interrupt vectors IV [1], IV [2], IV [3], IV [4] initialized by addresses of their corresponding ISR I =1..4. The elements of the hardware stack are a record R, where each field stores a specific CPU register (R.PC is the field, which stores the program counter PC and so on). The Hardware stack is manipulated using the standard stack operation Pop, Push, EmptyStack.a) Explain how the CPU detects an interrupt signal I and what actions should be taken?b) Write the initial and final sequences of instruction of a given ISR I (Transparency).c) Write the ISR4 such that whatever number of interrupted computation (in the stack) it gives the control to the first one interrupted.
b. Consider the extract from a C program below, explain what would happen to the other processes on the system if this code is run: i. On a pre-emptive multitasking operating system ii. On a co-operative multitasking operating system double h,w; char *p = ...; // Points to a block of memory to store the data for (h - 0; h < 600; h++) { double y = (h * (2.0 / 600.0)) - 1.0; for (w - 0; w < 800; wt+) double x = (w * (3.0 / 800.0)) - 1.5; int it - 4096; double r = 0, i - 0, r2 - 0, 12 - 0; do tmp - r2 - i2 + x; i - 2 *r * i+ y; r - tmp; r2 -r* r; 12 - i* i; } while( (r2 + i2) <- 4.0 66 (--it) !- 0); if(it 0) *p++ - 0; else *p++ - 255:
AziTech is considering the design of a new CPU for its new model of computer systems for 2021. It is considering choosing between two (2) CPU (CPUA and CPUB) implementationsbased on their performance. Both CPU are expected to have the same instruction set architecture. CPUA has a clock cycle time of 60 ns and CPUB has a clock cycle time of 75 ns. The same number of a particular instruction type is expected to be executed on both CPUsin order to determine which CPU would executes more instructions. CPUA is able to execute2MB of instructions in 5*106 clock cycles. CPUB executes the same number of instructions in 3*106 clock cycles.a) Using the MIPS performance metric, which of the two (2) CPU should be selected to be implemented in the new computer system. Justify your choice. b) Compute the execution time for both CPUs. Which CPU is faster?
in 80886 microprocessor What is result of executing the following instruction sequence? MOV BX, 100H MOV [ BX], 0C0ABH MOV AX, BX OR AL, [BX+1] AND AH, OFFH MOV [BX+2], AX HLT
Question 1 (Processes) a. A multi-programmed system with a single CPU has a very large number of CPU bound processes running on it that all have the same priority. Could you think of a CPU scheduling algorithm that would combine the lowest possible response times with the highest possible throughput and no starvation? Briefly explain your answer. b. Some operating systems force a context switch when a mutex (or spinlock) has been spin- ning for too long. List two reasons why this approach may be useful. c. This question relates to threads. Assume two user threads that increment a shared counter. The code runs on a multi-core system. Is it possible to obtain a concurrent implementation that is free of race conditions without using mutexes or semaphores (yes / no)? Briefly explain your answer. d. Figure 1 illustrates the times at which 10 different processes run on a single core of a single CPU. Every "row" represents a different process. The times increase towards the right, and…
3. Processor P has 2 real CPUS A and B. Each of these CPUS has one hyperthread HA and HB. Two separate threads T1 and T2 are scheduled by the OS to run on P. Explain an optimal schedule.
Suppose two secondary memory processes exist; wait to execute. In view of phase 1, the priority is high and the other priority is lowest. Just one process will simultaneously fit into the main memory. Explain how CPU is running on it? Can you describe the mechanism among all CPU components?
I need the answer as soon as possible