Ordinarily client programs are kept from dealing with I/0 straight by I/0 guidelines in them. For CPUS having express I/0 guidelines, such I/0 assurance is guaranteed by having the I/O directions favoured. In a CPU with memory planned I/0, there is no express I/0 guidance. Which one of coming up next is valid for a CPU with memory planned I/0? (a) 1/O insurance is guaranteed by operating system routine(s) (b) 1/O insurance is guaranteed by an equipment trap (c) I/O insurance is guaranteed during framework arrangement (d) 1/O insurance is unimaginable

Ordinarily client programs are kept from dealing with I/0 straight by I/0 guidelines in them. For CPUS having express I/0 guidelines, such I/0 assurance is guaranteed by having the I/O directions favoured. In a CPU with memory planned I/0, there is no express I/0 guidance. Which one of coming up next is valid for a CPU with memory planned I/0? (a) 1/O insurance is guaranteed by operating system routine(s) (b) 1/O insurance is guaranteed by an equipment trap (c) I/O insurance is guaranteed during framework arrangement (d) 1/O insurance is unimaginable

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Microprocessors 8086
b. Consider the extract from a C program below, explain what would happen to the other processes on the system if this code is run: i. On a pre-emptive multitasking operating system ii. On a co-operative multitasking operating system double h,w; char *p = ...; // Points to a block of memory to store the data for (h - 0; h < 600; h++) { double y = (h * (2.0 / 600.0)) - 1.0; for (w - 0; w < 800; wt+) double x = (w * (3.0 / 800.0)) - 1.5; int it - 4096; double r = 0, i - 0, r2 - 0, 12 - 0; do tmp - r2 - i2 + x; i - 2 *r * i+ y; r - tmp; r2 -r* r; 12 - i* i; } while( (r2 + i2) <- 4.0 66 (--it) !- 0); if(it 0) *p++ - 0; else *p++ - 255:
Question 1 (Processes) a. A multi-programmed system with a single CPU has a very large number of CPU bound processes running on it that all have the same priority. Could you think of a CPU scheduling algorithm that would combine the lowest possible response times with the highest possible throughput and no starvation? Briefly explain your answer. b. Some operating systems force a context switch when a mutex (or spinlock) has been spin- ning for too long. List two reasons why this approach may be useful. c. This question relates to threads. Assume two user threads that increment a shared counter. The code runs on a multi-core system. Is it possible to obtain a concurrent implementation that is free of race conditions without using mutexes or semaphores (yes / no)? Briefly explain your answer. d. Figure 1 illustrates the times at which 10 different processes run on a single core of a single CPU. Every "row" represents a different process. The times increase towards the right, and…
3. Processor P has 2 real CPUS A and B. Each of these CPUS has one hyperthread HA and HB. Two separate threads T1 and T2 are scheduled by the OS to run on P. Explain an optimal schedule.
i want all the staps Consider a computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of "6" addressing modes, and it has “50" computer registers. The computer supports instructions, where each instruction consists of following fields: • Mode • Operation code • Register • Register • Memory Address Given that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction
Single-chip computers are becoming increasingly limited by the access constraints to off-chip memory. To achieve high performance, the structure of on-chip memory must be appropriate, and it must be allocated effectively to minimize off-chip communication. We report experiments that demonstrate that on-chip memory can be effective for local variable accesses. For best use of the limited on-chip area, we suggest organizing memory as registers and argue that an effective register spilling scheme is required. We introduce a heuristic algorithm for register spilling within basic blocks and demonstrate that trace optimization techniques can extend the use of the algorithm to global allocation. Through trace simulation, we show that the use of registers can be more effective in reducing the bus traffic than cache memory of the same size Based on the issue above explain i) How the cache works ii) How it improve the computer PERFORMANCE. i) Explain the advantages and disadvantages of using a…
You are given the following data about a virtual memory system:(a) The TLB can hold 512 entries and can be accessed in 1 clock cycle (1nsec).(b) A page table entry can be found in 100 clock cycles or 100 nsec.(c) The average page replacement time is 9 msec.If page references are handled by the TLB 99% of the time, and only 0.01%lead to a page fault, what is the effective address-translation time?
Answer the following: A section of the memory space with the address from 0x6000 to 0x9FFF needs to be fully partitioned to two peripherals with the same memory size. The first peripheral's address starts at Ox6000 and ends at Ox . The second peripheral's address starts at Ox ends at Ox9FFF. and In embedded programming, let i = 13, then j =i<< 2; we have j = 0x wise operation, let i = 0x00ff and then i &= ~0x0010, we have i = Ox . And for bit-
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