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Modify the VHDL code below by adding a parameter that sets the number of flip-flops in the counter. LIBRARY ieee ; USE ieee.std logic.1164.all ; USE ieee.std logic_unsigned.all ; ENTITY upcount IS PORT ( Clock, Resetn, E : IN STD.LOGIC ; Q : OUT STD LOGIC-VECTOR (3 DOWNTO 0)) ; END upcount ; ARCHITECTURE Behavior OF upcount IS SIGNAL Count : STD.LOGIC.VECTOR (3 DOWNTO 0) ; BEGIN PROCESS ( Clock, Resetn ) BEGIN IF Resetn = '0' THEN Count <= "0000"; ELSIF (Clock'EVENT AND Clock = 'l') THEN IF E = '1' THEN Count <= Count +13; ELSE Count <= Count ; END IF ; END IF ; END PROCESS ; Q <= Count ; END Behavior ;

Modify the VHDL code below by adding a parameter that sets the number of flip-flops in the counter. LIBRARY ieee ; USE ieee.std logic.1164.all ; USE ieee.std logic_unsigned.all ; ENTITY upcount IS PORT ( Clock, Resetn, E : IN STD.LOGIC ; Q : OUT STD LOGIC-VECTOR (3 DOWNTO 0)) ; END upcount ; ARCHITECTURE Behavior OF upcount IS SIGNAL Count : STD.LOGIC.VECTOR (3 DOWNTO 0) ; BEGIN PROCESS ( Clock, Resetn ) BEGIN IF Resetn = '0' THEN Count <= "0000"; ELSIF (Clock'EVENT AND Clock = 'l') THEN IF E = '1' THEN Count <= Count +13; ELSE Count <= Count ; END IF ; END IF ; END PROCESS ; Q <= Count ; END Behavior ;

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...
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Modify the VHDL code below by adding a parameter that sets the number of flip-flops in the counter. LIBRARY ieee ; USE ieee.std logic_1164.all ; USE ieee.std logic unsigned.all ; ENTITY upcount IS PORT ( Clock, Resetn, E : IN STD.LOGIC ; : OUT STD.LOGIC-VECTOR (3 DOWNTO 0)) ; END upcount ; ARCHITECTURE Behavior OF upcount IS SIGNAL Count : STD.LOGIC-VECTOR (3 DOWNTO 0); BEGIN PROCESS ( Clock, Resetn ) BEGIN IF Resetn = '0' THEN Count <= "0000'" ; ELSIF (Clock'EVENT AND Clock = 'l') THEN IF E = '1' THEN Count <= Count +1; ELSE Count <= Count ; END IF ; END IF ; END PROCESS; Q <= Count ; END Behavior ;
Transcribed Image Text:Modify the VHDL code below by adding a parameter that sets the number of flip-flops in the counter. LIBRARY ieee ; USE ieee.std logic_1164.all ; USE ieee.std logic unsigned.all ; ENTITY upcount IS PORT ( Clock, Resetn, E : IN STD.LOGIC ; : OUT STD.LOGIC-VECTOR (3 DOWNTO 0)) ; END upcount ; ARCHITECTURE Behavior OF upcount IS SIGNAL Count : STD.LOGIC-VECTOR (3 DOWNTO 0); BEGIN PROCESS ( Clock, Resetn ) BEGIN IF Resetn = '0' THEN Count <= "0000'" ; ELSIF (Clock'EVENT AND Clock = 'l') THEN IF E = '1' THEN Count <= Count +1; ELSE Count <= Count ; END IF ; END IF ; END PROCESS; Q <= Count ; END Behavior ;
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