Simulate in LTSPICE Please, model file is as under:.model nch_lev2 NMOS (LEVEL=2 VTo=1.4 Kp=.6m LAMBDA=0.005 Cbd=100f Cbs=100f) VDD = 5 VWLVout+RsV inFigure 2 ] We wish to design the CMOS common-drain amplifier shown in Fig. 2 so that Ip = 200 µA,Im = 2 ms, and the de output voltage is 2.0V. Setting the transistor length to 2µm and usingthe given model parameters find the values of Rs, the transistor width, and the de inputvoltage.] Run the dc operating point analysis and verify that the design parameters specfieid in [Sim4.] are realized. Note the small-signal parameters and device capacitances Cgs, Cgd, Cbs, andCbd and then estimate the dominant pole of the amplifier.

Given: To design the CMOS and run the dc operating analysis using the diagram as,

Answered: m LAMBDA=0.005 Cbd

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