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Listing 5-3: Verilog design of FSM2 using two-segment coding style module FSM2 (A, CLK, reset, Z) input A, CLK, reset output Z reg [1:0] y, Y parameter [1:0] SO = 0, S1=1, S2 2, S3 = 3; always @ (negedge reset or negedge CLK) if (reset D else y <= Y always @ (y or A) begin case (y) / define STATE REG 0) y <= S0; l define NS LOGIC and OUTPUT LOG OS if (A-=1) begin Y = S3; Z 1, end else begin Y = S0; Z = 0; end if (A==1) begin Y= S0; Z= 1; end else begin Y = S1; Z 0, epd S2 if (A==1) begin Y= S1; 2=0 end else begin Y = S2 Z 0 end S3 if A==1) begin Y = S1; 2= 01 end else begin Y = S2 Z 0, end pune endmodule

Listing 5-3: Verilog design of FSM2 using two-segment coding style module FSM2 (A, CLK, reset, Z) input A, CLK, reset output Z reg [1:0] y, Y parameter [1:0] SO = 0, S1=1, S2 2, S3 = 3; always @ (negedge reset or negedge CLK) if (reset D else y <= Y always @ (y or A) begin case (y) / define STATE REG 0) y <= S0; l define NS LOGIC and OUTPUT LOG OS if (A-=1) begin Y = S3; Z 1, end else begin Y = S0; Z = 0; end if (A==1) begin Y= S0; Z= 1; end else begin Y = S1; Z 0, epd S2 if (A==1) begin Y= S1; 2=0 end else begin Y = S2 Z 0 end S3 if A==1) begin Y = S1; 2= 01 end else begin Y = S2 Z 0, end pune endmodule

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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DERIVE THE ASM FROM THE VERILG CODE
Listing 5-3: Verilog design of FSM2 using two-segment coding style module FSM2 (A, CLK, reset, Z), input A, CLK, reset output Z reg [1:0] y, Y parameter [1:0] SO =0, S1 =1, S2 = 2, S3 = 3; always @ (negedge reset or negedge CLK) if (reset 0) y <= S0 else y <= Y always @ (y or A) begin case (y) 1 define STATE REG / define NS LOGIC and OUTPUT LOG OS if (A 1) begin Y = S3; Z 1, end else begin Y = S0; Z= 0; end if (A=1) begin Y=S0; Z=1; end else begin Y =S1, Z 0, end if (A--1) begin Y = S1 2=0 else begin Y = S2 Z 0 end S3 if A==1) begin Y = S1;2=0 end else begin Y = S2; Z 0, end pue endmodule
Transcribed Image Text:Listing 5-3: Verilog design of FSM2 using two-segment coding style module FSM2 (A, CLK, reset, Z), input A, CLK, reset output Z reg [1:0] y, Y parameter [1:0] SO =0, S1 =1, S2 = 2, S3 = 3; always @ (negedge reset or negedge CLK) if (reset 0) y <= S0 else y <= Y always @ (y or A) begin case (y) 1 define STATE REG / define NS LOGIC and OUTPUT LOG OS if (A 1) begin Y = S3; Z 1, end else begin Y = S0; Z= 0; end if (A=1) begin Y=S0; Z=1; end else begin Y =S1, Z 0, end if (A--1) begin Y = S1 2=0 else begin Y = S2 Z 0 end S3 if A==1) begin Y = S1;2=0 end else begin Y = S2; Z 0, end pue endmodule
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