Let's pretend that the number of usable cores in central processing units (CPUs) is doubled every 18 months. In order to maintain the current level of per-core performance, how much more off-chip memory bandwidth would a CPU launched in three years need?

Let's pretend that the number of usable cores in central processing units (CPUs) is doubled every 18 months. In order to maintain the current level of per-core performance, how much more off-chip memory bandwidth would a CPU launched in three years need?

Name: Let's pretend that the number of usable cores in central processing u
Uploaded: 2024-03-20T06:51:23.000Z
Channel: Bartleby
Description: Let's pretend that the number of usable cores in central processing units (CPUs) is doubled every18 months. In order to maintain the current level of per-core performance, how much more off-chipmemory bandwidth would a CPU launched in three years ne

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter5: Data Storage Technology

Section: Chapter Questions

Problem 2PE

See similar textbooks

Similar questions

We may assume that the number of accessible cores in modern CPUs is doubled with each new generation every 18 months. How much more off-chip memory bandwidth would a CPU released in three years need in order to maintain the same per-core performance?
Let's pretend that the number of available cores in CPUs increases by one with each new generation, about every 18 months. If we fast forward three years, how much off-chip memory bandwidth would a CPU require to maintain the same per-core speed?
Let's pretend that the number of usable cores in central processing units (CPUs) is doubled every 18 months. How much more off-chip memory bandwidth would a CPU released in three years need in order to maintain the same per-core performance?
please answer with proper explanation and step by step solution. Question As a simple model of a bus-based multiprocessor system without caching, suppose that one instruction in every four references memory, and that a memory reference occupies the bus for an entire instruction time. If the bus is busy, the requesting CPU is put into a FIFO queue. How much faster will a 64-CPU system run than a 1-CPU system? Note: Don't copy paste from online website.
Let's pretend that the number of usable cores in central processing units (CPUs) is doubled with each new CPU generation every 18 months. If a CPU is released in three years, how much off-chip memory bandwidth will it need to maintain the same per-core performance?
Let's pretend that every 18 months a new generation of CPUs comes out that has twice as many cores as the last. How much more off-chip memory bandwidth will be needed for a CPU to be released in three years if per-core performance is to remain unchanged?
Suppose the number of available cores in CPUs is doubled every 18 months as technology advances. What is the minimum amount of off-chip memory bandwidth that the CPU of the future will need in order to keep per-core performance at the same level?
Consider a 32-bit microprocessor, with a 16-bit external data bus, driven by an 8-MHz input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals four input clock cycles. What is the maximum data transfer rate across the bus that this microprocessor can sustain in bytes/s? To increase its performance, would it be better to make its external data bus 32 bits or to double the external clock fre- quency supplied to the microprocessor? State any other assumptions you make and explain. Hint: Determine the number of bytes that can be transferred per bus cycle.
Suppose cache has a hit rate of 0.89 and access time of 5ns, main memory has a hit rate of 0.98 and access time of 60ns, and virtual memory has an access time of 700 us (microseconds). What is the average memory access time in us?
Let's assume that a new generation of CPUs with twice as many cores is released every 18 months. How much additional off-chip memory bandwidth will a CPU require in three years to maintain the same per-core performance?
Consider a computer with cache, DRAM, HDD memory hierarchy. The hit rate of cache is 90% and DRAM is 95%. Read latencies of cache, DRAM, and HDD are 5ns, 100ns, and 1ms respectively. What is the average latency of executing an instruction involving a memory read? Express your answer in micro-seconds. Round it to the nearest integer. Enter your answer here
A program sees a 4% miss rate on both the Instruction Cache and the Data Cache. Every instruction requires access to the Instruction cache. Only 35% of the instructions require data access from the Data Cache. The miss penalty for either the data or the instruction cache is 100 cycles. Assume the average Clocks per Instruction (CPI) is 2 without any memory stalls (this is a hypothetical machine where if there were no misses on that instruction, it would get executed in 2 clock cycles. We are not worrying about how it is implemented, just, that suppose it was possible). Assume the number of instructions in a program is X. F3: What is the total run time of the program including the missed cycles dues to data and instruction misses? F4: What is the ratio of the actual run time (from question F3 above) to the fictitious run time if there were no cache misses at all?