Juestion (a) We know that IpSI5 = IDSI8 = IpS19 = IB, and that these currents are all determined by M18, M19 and Rg such that %3D 2 WIL W/L9-1 2. I, BRWs/L 18 Rearranging the formula for W18, and taking into account that L18 = L19, We get Wis =W19/ (R, 21,Bo+ 10µ/(2k*N(200µ*2m)+1)° = 51.3 µm. %3D
Juestion (a) We know that IpSI5 = IDSI8 = IpS19 = IB, and that these currents are all determined by M18, M19 and Rg such that %3D 2 WIL W/L9-1 2. I, BRWs/L 18 Rearranging the formula for W18, and taking into account that L18 = L19, We get Wis =W19/ (R, 21,Bo+ 10µ/(2k*N(200µ*2m)+1)° = 51.3 µm. %3D
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
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Explain how they got this answer break down simply?

Transcribed Image Text:Figure 1 shows a complete op-amp circuit with an output load RL. The design has the
following properties.
VDD = 5 V, VSS 0 V and VR = 2.5 V.
L for all transistors (NMOS and PMOS) = 1 µm.
For the NMOS B= 0.002 A/V when W 10 um.
For the PMOS B- 0.002 A/V when W = 30 um.
The NMOS threshold voltage is 0.5 V and the PMOS threshold voltage is -0.5 V.
The bias current in Rg 100 µA.
You may assume that all the transistors are in saturation and that the Early voltage is 20 V.
VDD
M14
M15
M11
M12
M10
M16 H
M17
Vo
CM
Vi1
M2 b v2 HH
M1
M9
M18
M19
RL
M13
MB
RB
M4
M5
M3
VR
Figure 1. A three-stage op-amp with bias reference and Miller compensation.
Question 1. DC bias calculations.
What is the width (W) of M18 if Rg 2k0?
a.

Transcribed Image Text:Question 1
(a)
We know that Ips15 = Ipsis = IDS19 = IB, and that these currents are all determined by M18,
M19 and RB such that
2
21
W,/L
19
-1
BR Wis /LS
Rearranging the formula for Wis, and taking into account that L18 = L19, we get
%3D
Wis = W19/ (R, 21,B, +1)
10µ/(2k*N(200µ*2m)+1)° = 51.3 µm.
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