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It is required to design a combinational circuit that has three inputs A, B, and C and a single output Y such that Q.1. Y=ABC + A'B'C' (i) Derive the truth table of the circuit (ii) Draw the circuit diagram (hint: You can use LogicWorks or Logisim) (iii) Write a Verilog model to model the gate level design of the circuit using the primitive gates: AND, OR, and NOT gates. Model the delay of each gate function of its input i.e., the delay of a NOT gate is 1 delay-unit, the delay of a 2- input gate is 2 delay-units, and the delay of a 3-input gate is 3 delay-units. a

It is required to design a combinational circuit that has three inputs A, B, and C and a single output Y such that Q.1. Y=ABC + A'B'C' (i) Derive the truth table of the circuit (ii) Draw the circuit diagram (hint: You can use LogicWorks or Logisim) (iii) Write a Verilog model to model the gate level design of the circuit using the primitive gates: AND, OR, and NOT gates. Model the delay of each gate function of its input i.e., the delay of a NOT gate is 1 delay-unit, the delay of a 2- input gate is 2 delay-units, and the delay of a 3-input gate is 3 delay-units. a

Power System Analysis and Design (MindTap Course List)
Power System Analysis and Design (MindTap Course List)
6th Edition
ISBN:9781305632134
Author:J. Duncan Glover, Thomas Overbye, Mulukutla S. Sarma
Publisher:J. Duncan Glover, Thomas Overbye, Mulukutla S. Sarma
Chapter6: Power Flows
Section: Chapter Questions
Problem 6.15P
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It is required to design a combinational circuit that has three inputs A, B, and C and a single output Y such that Q.1. Y=ABC + A'B'C' (i) Derive the truth table of the circuit (ii) Draw the circuit diagram (hint: You can use LogicWorks or Logisim) (iii) Write a Verilog model to model the gate level design of the circuit using the primitive gates: AND, OR, and NOT gates. Model the delay of each gate function of its input i.e., the delay of a NOT gate is 1 delay-unit, the delay of a 2- input gate is 2 delay-units, and the delay of a 3-input gate is 3 delay-units. a (iv) Determine the longest delay of your cireuit. (v) Write a test bench to test the correctness of your Verilog model by applying all the possible input patterns. Apply consecutive inputs patterns after a delay of 10 delay- units. Verify the correctness of your computed longest delay in (iv). (vi) Write a second Verilog model to model the circuit using the assign statement to model the equation of the circuit. Use your computed delay in (iv) as the delay of your circuit. (vii) Use the test bench in (v) to test the correctness of your second Verilog model.
Transcribed Image Text:It is required to design a combinational circuit that has three inputs A, B, and C and a single output Y such that Q.1. Y=ABC + A'B'C' (i) Derive the truth table of the circuit (ii) Draw the circuit diagram (hint: You can use LogicWorks or Logisim) (iii) Write a Verilog model to model the gate level design of the circuit using the primitive gates: AND, OR, and NOT gates. Model the delay of each gate function of its input i.e., the delay of a NOT gate is 1 delay-unit, the delay of a 2- input gate is 2 delay-units, and the delay of a 3-input gate is 3 delay-units. a (iv) Determine the longest delay of your cireuit. (v) Write a test bench to test the correctness of your Verilog model by applying all the possible input patterns. Apply consecutive inputs patterns after a delay of 10 delay- units. Verify the correctness of your computed longest delay in (iv). (vi) Write a second Verilog model to model the circuit using the assign statement to model the equation of the circuit. Use your computed delay in (iv) as the delay of your circuit. (vii) Use the test bench in (v) to test the correctness of your second Verilog model.
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