1. The synchronous finite state machine (FSM) with input X and output Z consisted of two D-flip-flops withpositive edge triggering and asynchronous clear (Figure 1). The flip-flop input excitation and output forminglogic were implemented with 2-to-1 multiplexers (note that in the multiplexer symbols data inputs DO areshown above inputs D1). Obtain the following:a) Excitation equations for flip-flop inputs (Q1*, Q0*) and the equation for output Z.b) Output type (Moore/Mealy).c) State table: next states (Q1*, Q0*) as functions of present states (Q1, QO) and X, show output Z values.d) State diagram: show output Z values.e) Output Z sequence for input sequence X = 1111110000. The flip-flops were cleared initially.f) An estimate of the maximum clock frequency for reliable operation. The setup time and D to Qpropagation time are 6 and 55 ns, respectively. The multiplexer delays are 36 ns and 47 ns for Data andSelect inputs, respectively. Assume a 10 ns delay for the inverter.U1DDFFDOQ1'XDCLKDCLRDDOQCDCLOCKU2DDFFDCLOCKQHCLEARaQ1DOD1GNDQO

input X and output 2 consisted of two D-flip-flops with The synchronous finite state machine (FSM) positive edge triggering and asynchronous clear (Figure 1). The flip-flop input excitation and output form logic were implemented with 2-to-1 multiplexers (note that in the multiplexer symbols data inputs DO are shown above inputs D1). Obtain the following: a) Excitation equations for flip-flop inputs (Q1*, QO*) and the equation for output Z. b) Output type (Moore/Mealy). c) State table: next states (Q1*, QO*) as functions of present states (Q1, QO) and X, show output Z values. d) State diagram: show output Z values. e) Output Z sequence for input sequence X = 1111110 000. The flip-flops were cleared initially. f) An estimate of the maximum clock frequency for reliable operation. The setup time and D to Q propagation time are 6 and 55 ns, respectively. The multiplexer delays are 36 ns and 47 ns for Data an Select inputs, respectively. Assume a 10 ns delay for the inverter. U1DDFF Q1 -Dor XI CLKD CLRD DO DO Q0* HD CLOCK CLEAR U2DDFF D CLOCK CLEAR+ OH Q1 DO GND QO Z

input X and output 2 consisted of two D-flip-flops with The synchronous finite state machine (FSM) positive edge triggering and asynchronous clear (Figure 1). The flip-flop input excitation and output form logic were implemented with 2-to-1 multiplexers (note that in the multiplexer symbols data inputs DO are shown above inputs D1). Obtain the following: a) Excitation equations for flip-flop inputs (Q1, QO) and the equation for output Z. b) Output type (Moore/Mealy). c) State table: next states (Q1, QO) as functions of present states (Q1, QO) and X, show output Z values. d) State diagram: show output Z values. e) Output Z sequence for input sequence X = 1111110 000. The flip-flops were cleared initially. f) An estimate of the maximum clock frequency for reliable operation. The setup time and D to Q propagation time are 6 and 55 ns, respectively. The multiplexer delays are 36 ns and 47 ns for Data an Select inputs, respectively. Assume a 10 ns delay for the inverter. U1DDFF Q1 -Dor XI CLKD CLRD DO DO Q0* HD CLOCK CLEAR U2DDFF D CLOCK CLEAR+ OH Q1 DO GND QO Z

Introductory Circuit Analysis (13th Edition)

13th Edition

ISBN:9780133923605

Author:Robert L. Boylestad

Publisher:Robert L. Boylestad

Chapter1: Introduction

Section: Chapter Questions

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Question

1. The synchronous finite state machine (FSM) with input X and output Z consisted of two D-flip-flops with
positive edge triggering and asynchronous clear (Figure 1). The flip-flop input excitation and output forming
logic were implemented with 2-to-1 multiplexers (note that in the multiplexer symbols data inputs DO are
shown above inputs D1). Obtain the following:
a) Excitation equations for flip-flop inputs (Q1*, Q0*) and the equation for output Z.
b) Output type (Moore/Mealy).
c) State table: next states (Q1*, Q0*) as functions of present states (Q1, QO) and X, show output Z values.
d) State diagram: show output Z values.
e) Output Z sequence for input sequence X = 1111110000. The flip-flops were cleared initially.
f) An estimate of the maximum clock frequency for reliable operation. The setup time and D to Q
propagation time are 6 and 55 ns, respectively. The multiplexer delays are 36 ns and 47 ns for Data and
Select inputs, respectively. Assume a 10 ns delay for the inverter.
U1DDFF
DO
Q1'
XD
CLKD
CLRD
DO
QC
D
CLOCK
U2DDFF
D
CLOCK
QH
CLEAR
a
Q1
DO
D1
GND
QO

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