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For this problem you are to design another sequence detector. Design constraints: 1. It must be a Moore machine. 2. The sequence e it must detect in a serial string of 1s and Os at input Y is "100". 3. You may assume that the values arriving at input Y are properly synchronized with the clock. 4. The output must be Z = 1 when the prescribed sequence is detected, and 0 otherwise. 5. The circuit does not have to automatically reset when a 1 output occurs. (Return to initial state only when appropriate for sequence detection.) 6. It is possible to implement the design with only four states and two flip-flops. Since we generally do not want to implement designs that require more resources than are necessary, you MUST not use more than two flip-flops in your design. 7. Name the flip-flops A and B, and use the following state-name definitions: So (AB=00), S₁ (AB = 01), S₂ (AB = 10), S3 (AB = 11) 8. Use So for the initial state. It is up to you to decide what each of the other state-names mean with respect to the input sequence. Since you have some freedom of choice you must clearly articulate what each state-name means. See of the lecture, for example. 9. Logic must be implemented with no more than two levels and use only AND gates and OR gates (and a single inverter if you need to generate Y' from the Y input). Please submit: a) Your design for the State Graph, with documentation of what each State means (see item 8 above). b) Corresponding State Table c) Corresponding Transition Table d) Corresponding flip-flop Next-State Maps and expressions derived therefrom. e) Circuit diagram ps. The Mealy machine sequence detector described in lecture only required three states. But as mentioned in an earlier lecture, it is typical for a Moore machine to require more states to accomplish the same task.

For this problem you are to design another sequence detector. Design constraints: 1. It must be a Moore machine. 2. The sequence e it must detect in a serial string of 1s and Os at input Y is "100". 3. You may assume that the values arriving at input Y are properly synchronized with the clock. 4. The output must be Z = 1 when the prescribed sequence is detected, and 0 otherwise. 5. The circuit does not have to automatically reset when a 1 output occurs. (Return to initial state only when appropriate for sequence detection.) 6. It is possible to implement the design with only four states and two flip-flops. Since we generally do not want to implement designs that require more resources than are necessary, you MUST not use more than two flip-flops in your design. 7. Name the flip-flops A and B, and use the following state-name definitions: So (AB=00), S₁ (AB = 01), S₂ (AB = 10), S3 (AB = 11) 8. Use So for the initial state. It is up to you to decide what each of the other state-names mean with respect to the input sequence. Since you have some freedom of choice you must clearly articulate what each state-name means. See of the lecture, for example. 9. Logic must be implemented with no more than two levels and use only AND gates and OR gates (and a single inverter if you need to generate Y' from the Y input). Please submit: a) Your design for the State Graph, with documentation of what each State means (see item 8 above). b) Corresponding State Table c) Corresponding Transition Table d) Corresponding flip-flop Next-State Maps and expressions derived therefrom. e) Circuit diagram ps. The Mealy machine sequence detector described in lecture only required three states. But as mentioned in an earlier lecture, it is typical for a Moore machine to require more states to accomplish the same task.

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
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For this problem you are to design another sequence detector. Design constraints: 1. It must be a Moore machine. 9. Logic must be implemented with no more than two levels and use only AND gates and OR gates (and a single inverter if you need to generate Y' from the Y input). Please submit: a) Your design for the State Graph, with documentation of what each State means (see item 8 above). 2. The sequence it must detect in a serial string of 1s and Os at input Y is "100". 3. You may assume that the values arriving at input Y are properly synchronized with the clock. 4. The output must be Z 1 when the prescribed sequence is detected, and 0 otherwise. = 5. The circuit does not have to automatically reset when a 1 output occurs. (Return to initial state only when appropriate for sequence detection.) 6. It is possible to implement the design with only four states and two flip-flops. Since we generally do not want to implement designs that require more resources than are necessary, you MUST not use more than two flip-flops in your design. 7. Name the flip-flops A and B, and use the following state-name definitions: So (AB = 00), S₁ (AB 01), S₂ (AB = 10), S3 (AB = 11) 8. Use So for the initial state. It is up to you to decide what each of the other state-names mean with respect to the input sequence. Since you have some freedom of choice you must clearly articulate what each state-name means. See of the lecture, for example. b) Corresponding State Table c) e) Corresponding Transition Table d) Corresponding flip-flop Next-State Maps and expressions derived therefrom. Circuit diagram ps. The Mealy machine sequence detector described in lecture only required three states. But as mentioned in an earlier lecture, it is typical for a Moore machine to require more states to accomplish the same task.
Transcribed Image Text:For this problem you are to design another sequence detector. Design constraints: 1. It must be a Moore machine. 9. Logic must be implemented with no more than two levels and use only AND gates and OR gates (and a single inverter if you need to generate Y' from the Y input). Please submit: a) Your design for the State Graph, with documentation of what each State means (see item 8 above). 2. The sequence it must detect in a serial string of 1s and Os at input Y is "100". 3. You may assume that the values arriving at input Y are properly synchronized with the clock. 4. The output must be Z 1 when the prescribed sequence is detected, and 0 otherwise. = 5. The circuit does not have to automatically reset when a 1 output occurs. (Return to initial state only when appropriate for sequence detection.) 6. It is possible to implement the design with only four states and two flip-flops. Since we generally do not want to implement designs that require more resources than are necessary, you MUST not use more than two flip-flops in your design. 7. Name the flip-flops A and B, and use the following state-name definitions: So (AB = 00), S₁ (AB 01), S₂ (AB = 10), S3 (AB = 11) 8. Use So for the initial state. It is up to you to decide what each of the other state-names mean with respect to the input sequence. Since you have some freedom of choice you must clearly articulate what each state-name means. See of the lecture, for example. b) Corresponding State Table c) e) Corresponding Transition Table d) Corresponding flip-flop Next-State Maps and expressions derived therefrom. Circuit diagram ps. The Mealy machine sequence detector described in lecture only required three states. But as mentioned in an earlier lecture, it is typical for a Moore machine to require more states to accomplish the same task.
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