In a register/memory type CPU, the instruction lengths are typically variable. This presents a problem when the program is incremented during the Fetch-Decode-Execute cycle. What statements(s) is/are NOT TRUE with regard to Program Counter (PC) incrementing? Select one or more A. The binary loader overcomes the problem by positioning instructions at word boundaries so that PC can be calculated. B . PC is incremented by the largest possible foxed value, irrespective of the variability of the instruction C. Increment value is known when the current instruction has completed execution. D. increment value is known when the current instruction is decoded with the Instruction Register (IR) E. PC incrementing method is implementation dependent
In a register/memory type CPU, the instruction lengths are typically variable. This presents a problem when the program is incremented during the Fetch-Decode-Execute cycle. What statements(s) is/are NOT TRUE with regard to Program Counter (PC) incrementing?
Select one or more
A. The binary loader overcomes the problem by positioning instructions at word boundaries so that PC can be calculated.
B . PC is incremented by the largest possible foxed value, irrespective of the variability of the instruction
C. Increment value is known when the current instruction has completed execution.
D. increment value is known when the current instruction is decoded with the Instruction Register (IR)
E. PC incrementing method is implementation dependent
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