In a binary number of 4 bits, the most significant bit has a weight of Select one: a. 20 b. 24 c. None d. 2 3 e. 22

Do the following addition and subtraction in 8-bit signed 2's complement. a. 19 - 15 = 10 b. 1915 10 c. 25-37, 10 10 = 10 d. 12-610 10 = = e. 45 +27= 10 10

3) For the circuit shown in the following figure, Io - I3 are inputs to the 4:1 multiplexer. R (MSB) and S are control bits. The output Y can be represented by Answer: P 13 1₂ 4:1 MUX B Io S1 So RS Y O PQ+PR+ P Q S OPQ+ PS + QRS O PQ R+PQR+ Q R S + PQRS OPQR+ PQRS + Q R S+PQ RS

Design counter that counts from 00 to 59, using the IC 74LS90 ripple counter and use two 7 segment display to display the result count. You can also use 7447 binary to 7-segment Display Decoder. i need the diagram of it

A- 1. AND 2. OR A B• 5. XOR A A- 3. NAND 4. NOR O 6. XNORO B 7. 8. A. Butter Inverting Butter Provide the output for the following operators:

Determine the expression is for the following circuit diagram

Carry generate (G) and carry propagate (P) are defined as follows: G =AB and P = A  B. a) Show the expressions for Sum and Carry-out of a 1-bit Full Adder (1bFA) in terms of Carry-In, P and G. b) Design the 1b FA with any number of 2-to-1 multiplexers. Show the schematic with inputs A, B, Carryin and outputs Sum and Carry-out. c) Estimate the following propagation delays for your schematic: • Carry-in to sum (t1), • Data-to-sum (t2), • Carry-in-to-Carry-out (t3), • Data to Carry-out (t4) Assume the following propagation delays: a 5 ns for data D1, D0 to output Y of 2-to1 mux, a 25 ns for select S to output Y, and a 10 ns delay for inverters.

can someone help me please and solve this questions with steps please

I need the answer as soon as possible

2)Convert 11011010100100012 to hexadecimal. A)895B B)CA11 C)53AC1 D)DA91