Carry generate (G) and carry propagate (P) are defined as follows: G =AB and P = A  B.  a) Show the expressions for Sum and Carry-out of a 1-bit Full Adder (1bFA) in terms of Carry-In, P and  G.  b) Design the 1b FA with any number of 2-to-1 multiplexers. Show the schematic with inputs A, B, Carryin and outputs Sum and Carry-out.  c) Estimate the following propagation delays for your schematic:  • Carry-in to sum (t1),  • Data-to-sum (t2),  • Carry-in-to-Carry-out (t3),  • Data to Carry-out (t4)  Assume the following propagation delays: a 5 ns for data D1, D0 to output Y of 2-to1 mux, a 25 ns for select  S to output Y, and a 10 ns delay for inverters.

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Carry generate (G) and carry propagate (P) are defined as follows: G =AB and P = A  B. 
a) Show the expressions for Sum and Carry-out of a 1-bit Full Adder (1bFA) in terms of Carry-In, P and 
G. 
b) Design the 1b FA with any number of 2-to-1 multiplexers. Show the schematic with inputs A, B, Carryin and outputs Sum and Carry-out. 
c) Estimate the following propagation delays for your schematic: 
• Carry-in to sum (t1), 
• Data-to-sum (t2), 
• Carry-in-to-Carry-out (t3), 
• Data to Carry-out (t4) 
Assume the following propagation delays: a 5 ns for data D1, D0 to output Y of 2-to1 mux, a 25 ns for select 
S to output Y, and a 10 ns delay for inverters. 

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