Answered: I need help with the questions below so…

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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I need help with the questions below so I have a direct-mapped cache, like in the images attached. Also, I need to know the cache size, block size, word size, index bits (log2 # of blocks), block offset bits (log2 # of words in a block), byte offset bits (log2 # of bytes in a word), and tag bits (# of address bits - (# of index bits+# of block offset bits+# of byte offset bits).

3.0 Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit hexadecimal memory addresses, given as byte addresses. 74, A0, 78, 38C, AC, 84, 88, 8C, 7C, 34, 38, 13C, 388, 18C

3.0.1 For each of these references, identify the index and the tag, given a direct-mapped cache with 8 one-word blocks. List if each reference is a hit or a miss, assuming the cache is initially empty and show every entry to the cache, including the tag value and the addresses of all data items stored. Use hexadecimal or binary, whichever is easier.

3.0.2 For each of these references, identify the index and the tag, given a direct-mapped cache with two word blocks and a total of 16 words. List if each reference is a hit or a miss, assuming the cache is initially empty and show every entry to the cache, including the tag value and the addresses of all data items stored. Use hexadecimal or binary, whichever is easier.

Direct Mapped Example
Consider a computer with a 256-byte address space (address = 8 bits) and a 32-byte
direct mapped cache. The computer word size is four bytes and each cache block
contains two words. If the cache is initially empty and the following sequence of
hexadecimal addresses is read, show the cache contents and the corresponding
sequence of hits and misses.
48, OC, 48, 4C, 5C, 3A, 20, 22, 24, 80, 48, 30, 34, 26, 3E, 24, 28, 2C, 40, 2E
32 bytes x 1 word/4 bytes x 1 block/2 words x 1 set/1 block = 4 sets
Index = 2 bits, Byte offset = 2 bits, Block offset = 1 bit, Tag = 8 - (2+2+1) = 8− 5 = 3
Set Tag
WNHO
0
2
Data

Direct Mapped Example - Address 5C check
32 bytes x 1 word/4 bytes x 1 block/2 words x 1 set/1 block = 4 sets
Index = 2 bits, Byte offset = 2 bits, Block offset = 1 bit, Tag = 8− (2 + 2 + 1) = 8− 5 = 3
48, 0C, 48, 4C, 5C, 3A, 20, 22, 24, 80, 48, 30, 34, 26, 3E, 24, 28, 2C, 40, 2E
Address 5C = 0101 1100 Miss
No
Match
Set
0
1
2
3
Tag (3 bits)
010
Tag
Index (2 bits) Block Offset (1 bit)
11
1
010, 000, 010
Data
Byte Offset (2 bits)
00
M[48..4F], M[08..OF], M[48..4F]

Expert Solution

Step 1: Determine Cache parameters

In order to determine the cache size, block size, word size, index bits, block offset bits, byte offset bits, and tag bits for a direct-mapped cache, It is important to analyze the cache configuration.

In the provided questions there are two different cache configurations, so calculate the parameters for each:

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