Given the execution of the below instructions (and initial state in memory): 0 MOV r1, #12; 1 ADD r2, r1,#10; 2 BL Loop; 3 LDR r5, 1234; 10 Loop: MOV r3, #1; |11 MUL r4, r2,r3 ; |12 MOV pc,lr ; If a set associative cache with 2 sets (set 1 and set 2) with 4 word size lines each(line 0-3) is used. What is the final instruction stored in the cache line 3, set 1? O MUL r4, r2,r3 O LDR r5, 1234 BL Loop O Loop MOV r3, #1

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Note: This is referring to ARM architecture.

### Instruction Execution and Memory State

Here is the sequence of assembly instructions and their memory addresses:

| Address | Instruction        |
|---------|--------------------|
| 0       | MOV r1, #12        |
| 1       | ADD r2, r1, #10    |
| 2       | BL Loop            |
| 3       | LDR r5, 1234       |
| 10      | Loop: MOV r3, #1   |
| 11      | MUL r4, r2, r3     |
| 12      | MOV pc, lr         |

### Cache Configuration

- **Type:** Set associative cache
- **Sets:** 2 (Set 1 and Set 2)
- **Line size:** 4 words (Lines 0-3)

### Question

Given the configuration of the cache, determine the final instruction stored in cache line 3, set 1.

### Options

- MUL r4, r2, r3
- LDR r5, 1234
- BL Loop
- Loop MOV r3, #1

The correct answer is the instruction at line 3, which would be stored in line 3 of set 1 within the cache.
Transcribed Image Text:### Instruction Execution and Memory State Here is the sequence of assembly instructions and their memory addresses: | Address | Instruction | |---------|--------------------| | 0 | MOV r1, #12 | | 1 | ADD r2, r1, #10 | | 2 | BL Loop | | 3 | LDR r5, 1234 | | 10 | Loop: MOV r3, #1 | | 11 | MUL r4, r2, r3 | | 12 | MOV pc, lr | ### Cache Configuration - **Type:** Set associative cache - **Sets:** 2 (Set 1 and Set 2) - **Line size:** 4 words (Lines 0-3) ### Question Given the configuration of the cache, determine the final instruction stored in cache line 3, set 1. ### Options - MUL r4, r2, r3 - LDR r5, 1234 - BL Loop - Loop MOV r3, #1 The correct answer is the instruction at line 3, which would be stored in line 3 of set 1 within the cache.
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