Given a 2-way set-associative cache with 2 entries (sets) and 1 byte block size (no offset), what is the LRU value of each entry (set) after the following processor access sequence? Assume the LRU bits of both entries are set to 0 initially. Processor accesses: 10000, 10001, 11101, 11011, 11110 LRU (entry 0) = _ LRU (entry 1) = O 1,0 O 0,0 O 0, 1 O 1,1

Given a 2-way set-associative cache with 2 entries (sets) and 1 byte block size (no offset), what is the LRU value of each entry (set) after the following processor access sequence? Assume the LRU bits of both entries are set to 0 initially. Processor accesses: 10000, 10001, 11101, 11011, 11110 LRU (entry 0) = _ LRU (entry 1) = O 1,0 O 0,0 O 0, 1 O 1,1

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Question

Given a 2-way set-associative cache with 2 entries (sets) and 1 byte block size (no offset), what is the LRU value of each entry (set) after the following processor
access sequence? Assume the LRU bits of both entries are set to 0 initially. Processor accesses: 10000, 10001, 11101, 11011, 11110
LRU (entry 0) = _, LRU (entry 1) =
O 1,0
O 0, 0
O 0, 1
O 1, 1

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Question 4
Cache system B represents a 2-way set-associative mapping cache system in table 2 The system is byte-addressable and the block size is one word (4 bytes). The tag and set numbers are represented with binary numbers. The contents of words in a block are represented with hexadecimal. Tag 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 Table 2 1. What is the size of the main memory for the Cache system B? Answer= 2. What is the size of the cache memory of Cache system B? Answer = Answer= Answer = 16 Answer = Set Number 16 1011 0110 1101 1011 0110 1101 miss(es) 1011 0110 1110 1011 0110 1110 1011 0110 1111 1011 0110 1111 1011 0111 0000 3. If we request to read memory address F1 24 2D B7, what data do we get? 1011 0111 0000 1011 0111 0001 1011 0111 0001 4. If we…
A 2-way set associative cache consists of four sets. Main memory contains 2K blocks of eight words each. Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes. Compute the hit ratio for a program that loops 6 times from locations 8 to 51 in main memory. You may leave the hit ratio in terms of a fraction. Please show details how you obtain the result.
3. The table below represents five lines from a cache that uses fully associative mapping with a block size of 8. Identify the address of the shaded data, 0xE6, first in binary and then in hexadecimal. The tag numbers and word id bits are in binary, but the content of the cache (the data) is in hexadecimal. Word id bits Tag 000 001 010 011 100 101 110 111 ------------------------------------------ 1011010 10 65 BA 0F C4 19 6E C3 1100101 21 76 CB 80 D5 2A 7F B5 0011011 32 87 DC 91 E6 3B F0 A6 1100000 43 98 ED A2 F7 4C E1 97 1111100 54 9A FE B3 08 5D D2 88
Consider a cache with 32KİB data, 16-word blocks, and 24-bit addresses, answer the following questions: a) For the direct-mapped configuration, determine the number of index bits and tag bits in the 24-bit address. b) For 4-way set associative configuration, determine the number of index bits and tag bits in the 24-bit address. c) For fully associative contiguration, determine the number of index bits and tag bits in the 24-bit address. d) For an 8-way set associative configuration, identify the set number in the cache to which the following 24-bit memory address maps: Ox001Z00 (Hexadecimal notation) where Z is the least significant digit in your student ID (written as a decimal number)
The low order 4 bits of the address indicate location in the cache line and the next 4 bits indicate which line in the cache should be used and the remaining bits of the address are used as the cache tag. If the following addresses are read in this order, indicate (circle or similar) each one that would result in a cache miss. 2A1220 2A122C B14408 B14428 2A122C
Given an 8-word, 4-way set associative cache, and the sequence of address accesses below, enter the number of misses. 22 24 22 13 13 22