For the logic circuit in Figure 2, suppose that the the propagation time of each logic gate is equal, and that the network is in the total state (x1x2, y) == (11, 1). Draw the timing diagrams for 2 and the outputs of the four logic gates when the input x2 changes values to '0’. Comment on the behaviour of the logical network. Y =x;%3 + %z*y, y

Computer Networking: A Top-Down Approach (7th Edition)
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For the logic circuit in Figure 2, suppose that the the propagation time of each
logic gate is equal, and that the network is in the total state (x1x2, y) == (11,1).
Draw the timing diagrams for x2 and the outputs of the four logic gates when
the input x2 changes values to '0'. Comment on the behaviour of the logical
network.
X1
X2
Y=x,%, + %,*y,
y
Figure 2: Logic Circuit Question IVa
Present
Next State
x1x2 = 00 | X1£2 = 01 | x1x2 =
Y
State
10
Tịx2 = 11
Y
Y
(0)
(1)
(0)
(1)
(0)
1
(1)
Table 2: Excitement Table IVa
Transcribed Image Text:For the logic circuit in Figure 2, suppose that the the propagation time of each logic gate is equal, and that the network is in the total state (x1x2, y) == (11,1). Draw the timing diagrams for x2 and the outputs of the four logic gates when the input x2 changes values to '0'. Comment on the behaviour of the logical network. X1 X2 Y=x,%, + %,*y, y Figure 2: Logic Circuit Question IVa Present Next State x1x2 = 00 | X1£2 = 01 | x1x2 = Y State 10 Tịx2 = 11 Y Y (0) (1) (0) (1) (0) 1 (1) Table 2: Excitement Table IVa
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