For the following problems assume 1 kilobyte (KB) = 1024 bytes and1 megabyte (MB) = 1024 kilobytes. For this problem, assume you have address translation hardware with the following properties: 1. • Virtual addresses, physical addresses, and page table entries are 32 bits wide. The page size in the system is 4 KB. A virtual address is a page number followed by a byte offset within the page. (a) How many bits of the virtual address must be used for the offset, so that every byte in the page can have a unique address? (b) How many bits are left over in the virtual address to store the page number? (c) How many different page numbers does an address space in this system support? (You can express this as a power of two) (d) If a page table consists of a page table entry for each page number in an address space, how much space in MB would the page table take up if it were stored in physical memory?

For the following problems assume 1 kilobyte (KB) = 1024 bytes and1 megabyte (MB) = 1024 kilobytes. For this problem, assume you have address translation hardware with the following properties: 1. • Virtual addresses, physical addresses, and page table entries are 32 bits wide. The page size in the system is 4 KB. A virtual address is a page number followed by a byte offset within the page. (a) How many bits of the virtual address must be used for the offset, so that every byte in the page can have a unique address? (b) How many bits are left over in the virtual address to store the page number? (c) How many different page numbers does an address space in this system support? (You can express this as a power of two) (d) If a page table consists of a page table entry for each page number in an address space, how much space in MB would the page table take up if it were stored in physical memory?

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Description: For the following problems assume 1 kilobyte (KB) = 1024 bytes and 1 megabyte (MB) =1024 kilobytes.%3D%3D1. For this problem, assume you have address translation hardware with the followingproperties:Virtual addresses, physical addresses, and page t

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Exercise 1: Consider a word-addressable memory of 16 GB, where each word is composed of 128 bits. This memory is directly mapped to a cache of 1 MB composed of blocks where each block contains 16 words. a) What is length (in bits) of the address provided by the processor? b) What is the length (in Bytes) of one memory block? c) How many lines does the cache have? d) What is the length (in bits) of each of the TAG, LINE, and OFFSET? e) Which line in cache can hold the address 00000FOF?