For the first part, you are going to write six functions. • unsigned int getL1SetID(u_int32_t address) returns the setID assocated with the input address for L1 cache. unsigned int getL1Tag(u_int32_t address) returns the tag assocated with the input ad- dress for L1 cache. • unsigned int getL2SetID(u_int32_t address) returns the setID assocated with the input address for L2 cache. • unsigned int getL2Tag (u_int32_t address) returns the tag assocated with the input ad- dress for L2 cache. • int Llaccess (u_int32_t address, int type, u_int32_t data) performs a L1 cache ac- cess. This function returns 1 if the input address is in the cache and 0 otherwise. Please note that this function UPDATE the cache content if we are writing to the cache. • int L2access (u_int32_t address, int type, u_int32_t data) performs a L2 cache ac- cess. This function returns 1 if the input address is in the cache and 0 otherwise. Please note that this function UPDATE the cache content if we are writing to the cache.

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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For the first part, you are going to write six functions.
• unsigned int getL1SetID(u_int32_t address) returns the setID assocated with the input
address for L1 cache.
• unsigned int getL1Tag (u_int32_t address) returns the tag assocated with the input ad-
dress for L1 cache.
unsigned int getL2SetID (u_int32_t address) returns the setID assocated with the input
address for L2 cache.
unsigned int getL2Tag (u_int32_t address) returns the tag assocated with the input ad-
dress for L2 cache.
• int Llaccess (u_int32_t address, int type, u_int32_t data) performs a L1 cache ac-
cess. This function returns 1 if the input address is in the cache and 0 otherwise. Please note
that this function UPDATE the cache content if we are writing to the cache.
• int L2access (u_int32_t address, int type, u_int32_t data) performs a L2 cache ac-
cess. This function returns 1 if the input address is in the cache and 0 otherwise. Please note
that this function UPDATE the cache content if we are writing to the cache.
Transcribed Image Text:For the first part, you are going to write six functions. • unsigned int getL1SetID(u_int32_t address) returns the setID assocated with the input address for L1 cache. • unsigned int getL1Tag (u_int32_t address) returns the tag assocated with the input ad- dress for L1 cache. unsigned int getL2SetID (u_int32_t address) returns the setID assocated with the input address for L2 cache. unsigned int getL2Tag (u_int32_t address) returns the tag assocated with the input ad- dress for L2 cache. • int Llaccess (u_int32_t address, int type, u_int32_t data) performs a L1 cache ac- cess. This function returns 1 if the input address is in the cache and 0 otherwise. Please note that this function UPDATE the cache content if we are writing to the cache. • int L2access (u_int32_t address, int type, u_int32_t data) performs a L2 cache ac- cess. This function returns 1 if the input address is in the cache and 0 otherwise. Please note that this function UPDATE the cache content if we are writing to the cache.
You will need a starter package, which ships in the form of a zip file.
Once extracted, you will find three files: cacheSim.h, cacheSim.c and input.trace.
Inside cacheSim.c, we have provided the skeleton code for our simple cache, which has the following
properties:
• The cache has two levels
• A cache block is 16 bytes.
Each address is accessing 1 bytes of data.
• The L1 cache is a 64 Bytes, 2-way set associative cache.
• The L2 cache is a 256 Bytes, 4-way set associative cache.
• The cache is inclusive, which mean that data in L1 cache will also remain in the L2 cache. In other
word, the data in L1 is a subset of the data in L2 (This assumption simplify your design).
• The cache is using a least recently used (LRU) cache replacement policy. Note that this is simpler
to implement than the LRU policy.
Transcribed Image Text:You will need a starter package, which ships in the form of a zip file. Once extracted, you will find three files: cacheSim.h, cacheSim.c and input.trace. Inside cacheSim.c, we have provided the skeleton code for our simple cache, which has the following properties: • The cache has two levels • A cache block is 16 bytes. Each address is accessing 1 bytes of data. • The L1 cache is a 64 Bytes, 2-way set associative cache. • The L2 cache is a 256 Bytes, 4-way set associative cache. • The cache is inclusive, which mean that data in L1 cache will also remain in the L2 cache. In other word, the data in L1 is a subset of the data in L2 (This assumption simplify your design). • The cache is using a least recently used (LRU) cache replacement policy. Note that this is simpler to implement than the LRU policy.
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