Finite state machine (FSM) counter design: Design a finite state machine that detects the following sequence of serial inputs on input A: 0111. The output Y should assert every time that sequence of bits is encountered in the input stream. You may assume that input A becomes a new value (i.e., the next bit) shortly after each clock edge. Show all the steps of FSM design from the black box and state transition diagram all the way to the circuit (and all the steps in between). Hint: For example, the following series of values on A could occur. After each sequence of the desired pattern (0111) is detected (highlighted in orange or green -- see attached), output Y should assert. A: 0101001110010111011100101001000100111111010111011010111011111110111011101
Finite state machine (FSM) counter design: Design a finite state machine that detects the following sequence of serial inputs on input A: 0111. The output Y should assert every time that sequence of bits is encountered in the input stream. You may assume that input A becomes a new value (i.e., the next bit) shortly after each clock edge.
Show all the steps of FSM design from the black box and state transition diagram all the way to the circuit (and all the steps in between).
Hint: For example, the following series of values on A could occur. After each sequence of the desired pattern (0111) is detected (highlighted in orange or green -- see attached), output Y should assert.
A: 0101001110010111011100101001000100111111010111011010111011111110111011101
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