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Figure Q4(a) shows a logic circuit which consists of a group of eight (8) individual 2-input logic gates with control bits inpu (x7-x0) that function to manipulate the input bits (b7 - bo) so that the output bits will result as shown on Figure Q4(b). Determine the logic gate used and its input control bits (x7 - x0). x7 b7 x6 b6 x5 b5 x4 b4 x3 b3 x2 b2 x1 b1 x0 b0 Logic Gate Logic Gate Logic Logic Gate Logic Gate Logic Gate Logic Gate Logic Gate Gate 8 7 4 3 1 b5 b4 b1' bo Figure Q4a input input control bit b7 b6 b5 b4 b3 b2 bl b0 x7 x6 x5 х4 x3 x2 xl x0 1 b5 b4 bl' b0" output b7 change to logic 1 b6 change to logic 1 b5 b4 b3 change b2 change to logic 0 bl b0 remains remains to logic 0 inverted inverted 0 0 0 0 1110 Logic ctrl input =x7 x6 x5 x4 x3 x2 x1 x0 Output = 1 10 0 0 0 0 1 Example 1: input b7 - b0 Example 2: input b7 – b0 = 1 1 1 10 00 1 x7 x6 x5 x4 x3 x2 x1 x0 Logic ctrl input Output 11110010 %3D

Figure Q4(a) shows a logic circuit which consists of a group of eight (8) individual 2-input logic gates with control bits inpu (x7-x0) that function to manipulate the input bits (b7 - bo) so that the output bits will result as shown on Figure Q4(b). Determine the logic gate used and its input control bits (x7 - x0). x7 b7 x6 b6 x5 b5 x4 b4 x3 b3 x2 b2 x1 b1 x0 b0 Logic Gate Logic Gate Logic Logic Gate Logic Gate Logic Gate Logic Gate Logic Gate Gate 8 7 4 3 1 b5 b4 b1' bo Figure Q4a input input control bit b7 b6 b5 b4 b3 b2 bl b0 x7 x6 x5 х4 x3 x2 xl x0 1 b5 b4 bl' b0" output b7 change to logic 1 b6 change to logic 1 b5 b4 b3 change b2 change to logic 0 bl b0 remains remains to logic 0 inverted inverted 0 0 0 0 1110 Logic ctrl input =x7 x6 x5 x4 x3 x2 x1 x0 Output = 1 10 0 0 0 0 1 Example 1: input b7 - b0 Example 2: input b7 – b0 = 1 1 1 10 00 1 x7 x6 x5 x4 x3 x2 x1 x0 Logic ctrl input Output 11110010 %3D

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Figure Q4(a) shows a logic circuit which consists of a group of eight (8) individual 2-input logic gates with control bits input (x7-x0) that function to manipulate the input bits (b7 - bo) so that the output bits will result as shown on Figure Q4(b). Determine the logic gate used and its input control bits (x7 - x0). x7 b7 x6 b6 x5 b5 x4 b4 x3 b3 x2 b2 х1 b1 x0 b0 Logic Logic Gate Logic Logic Logic Logic Gate Logic Gate Logic Gate Gate Gate Gate Gate 8. 7 4 2 1 1 b5 b4 b1' bo Figure Q4a input b7 b6 b5 b4 b3 b2 b1 b0 input control bit x7 x6 x5 x4 x3 x2 xl хо 1 1 b5 b4 bl' b0' b7 change b6 change to logic 1 output b5 b4 b3 change b2 change to logic 0 b1 b0 to logic 1 геmains to logic 0 remains inverted inverted Example 1: input b7 – b0 0 0 0 0 1110 Logic ctrl input =x7 x6 x5 x4 x3 x2 x1 x0 1 10 0 0 0 0 1 Example 2: input b7 – b0 = 1 11 1 000 1 Logic ctrl input =x7 x6 x5 x4 x3 x2 x1 x0 1 1110 0 1 0 %3! Output Output %3D Figure Q4b 6.
Transcribed Image Text:Figure Q4(a) shows a logic circuit which consists of a group of eight (8) individual 2-input logic gates with control bits input (x7-x0) that function to manipulate the input bits (b7 - bo) so that the output bits will result as shown on Figure Q4(b). Determine the logic gate used and its input control bits (x7 - x0). x7 b7 x6 b6 x5 b5 x4 b4 x3 b3 x2 b2 х1 b1 x0 b0 Logic Logic Gate Logic Logic Logic Logic Gate Logic Gate Logic Gate Gate Gate Gate Gate 8. 7 4 2 1 1 b5 b4 b1' bo Figure Q4a input b7 b6 b5 b4 b3 b2 b1 b0 input control bit x7 x6 x5 x4 x3 x2 xl хо 1 1 b5 b4 bl' b0' b7 change b6 change to logic 1 output b5 b4 b3 change b2 change to logic 0 b1 b0 to logic 1 геmains to logic 0 remains inverted inverted Example 1: input b7 – b0 0 0 0 0 1110 Logic ctrl input =x7 x6 x5 x4 x3 x2 x1 x0 1 10 0 0 0 0 1 Example 2: input b7 – b0 = 1 11 1 000 1 Logic ctrl input =x7 x6 x5 x4 x3 x2 x1 x0 1 1110 0 1 0 %3! Output Output %3D Figure Q4b 6.
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