Experiment No. I. SEQUENTIAL LOGIC CIRCUITS( Latches and Flip Flops) Object: To investigate the properties of logic circuit configurations which possess memory. Procedure: 1. Using the circuit shown in fig. (1-la), verify the truth table of the S-R flip- flop. 2. Realize the S-R flip-flop shown in fig. (1-la) using NOR gates only. Connect and verify operation. 3. Using the unit shown in fig. (1-6) find the truth table of the S-R, D-type, T- type and J-K type flip-flop. Fig. (1-1) shows the basic construction of an S-R (set-reset) flip-flop. (b) (a) SIR: Qn: On+1 ---:---:---- :0:0: O : 0:0: i 1 :0: 1:0 : 0: :0: 1: 1:0 : : 1:0: 0: 1: :1:0:1 : : 1:1: 0 : Do 1 : Do 1 a S.R flip-flop construction b. S.R flip-flop truth table. In S-R flip-flop truth table fig. (1-lb), Qn refers to the state of Q before the D-tyee Flie-fl op elock S-H Plip-Plop Symbol

Experiment No. I. SEQUENTIAL LOGIC CIRCUITS( Latches and Flip Flops) Object: To investigate the properties of logic circuit configurations which possess memory. Procedure: 1. Using the circuit shown in fig. (1-la), verify the truth table of the S-R flip- flop. 2. Realize the S-R flip-flop shown in fig. (1-la) using NOR gates only. Connect and verify operation. 3. Using the unit shown in fig. (1-6) find the truth table of the S-R, D-type, T- type and J-K type flip-flop. Fig. (1-1) shows the basic construction of an S-R (set-reset) flip-flop. (b) (a) SIR: Qn: On+1 ---:---:---- :0:0: O : 0:0: i 1 :0: 1:0 : 0: :0: 1: 1:0 : : 1:0: 0: 1: :1:0:1 : : 1:1: 0 : Do 1 : Do 1 a S.R flip-flop construction b. S.R flip-flop truth table. In S-R flip-flop truth table fig. (1-lb), Qn refers to the state of Q before the D-tyee Flie-fl op elock S-H Plip-Plop Symbol

Introductory Circuit Analysis (13th Edition)

13th Edition

ISBN:9780133923605

Author:Robert L. Boylestad

Publisher:Robert L. Boylestad

Chapter1: Introduction

Section: Chapter Questions

Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...

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