** Digital logic circuit analysis and design ** **variabel masukan : input variabel ** variabel luaran : output variabel ** variabel keadaan : state variabel In accordance with the state transition diagram above, perform the following analysis: a) Given input sequence BA = {00,11,11,00,11,10,11,00}. Synthesize using a timing chart, or table, to determine the string of each state variable and output variable. b) Given the input sequence BA = (00,11,11,11,11,11,11,00). Perform a synthesis to determine the string of each state variable and output variable. c) If the meaning of output (YX) is actually 00: not detect 01: is detecting 10: detected 11: the detection process repeats itself. Conclude, this system detects what input string?
** Digital logic circuit analysis and design **
**variabel masukan : input variabel
** variabel luaran : output variabel
** variabel keadaan : state variabel
In accordance with the state transition diagram above, perform the following analysis:
a) Given input sequence BA = {00,11,11,00,11,10,11,00}. Synthesize using a timing chart, or table, to determine the string of each state variable and output variable.
b) Given the input sequence BA = (00,11,11,11,11,11,11,00). Perform a synthesis to determine the string of each state variable and output variable.
c) If the meaning of output (YX) is actually
00: not detect
01: is detecting
10: detected
11: the detection process repeats itself. Conclude, this system detects what input string?
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