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Q2/ Choose five only 1-A stage in shift register consist of a) latch b) Flip flop c) Byte of storage 2-a modulus 10-johanson counter requires a) ten flip-flop b) four flip_flop c) five flip_flop 3-A PAL consist of a a) Programmable AND array and programmable OR array b) Programmable AND array and a fixed OR array c) Fixed AND/OR array 4- if an S_R latch has a 1 on the S input and a 0 on the are input and then the input goes to 0, the latch will be a) set b) RESET c) CLEAR

Q2/ Choose five only 1-A stage in shift register consist of a) latch b) Flip flop c) Byte of storage 2-a modulus 10-johanson counter requires a) ten flip-flop b) four flip_flop c) five flip_flop 3-A PAL consist of a a) Programmable AND array and programmable OR array b) Programmable AND array and a fixed OR array c) Fixed AND/OR array 4- if an S_R latch has a 1 on the S input and a 0 on the are input and then the input goes to 0, the latch will be a) set b) RESET c) CLEAR

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...
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Q2/ Choose five only 1-A stage in shift register consist of a) latch b) Flip flop c) Byte of storage 2-a modulus 10-johanson counter requires a) ten flip-flop b) four flip_flop c) five flip_flop 3-A PAL consist of a a) Programmable AND array and programmable OR array b) Programmable AND array and a fixed OR array c) Fixed AND/OR array 4- if an S_R latch has a 1 on the S input and a 0 on the are input and then the input goes to 0 , the latch will be a) set b) RESET c) CLEAR 5-Type of PLD programmable link process technologies are a) EEPROM b) ROM c) antifuse d) both A and C 6-VHSIC stands for (a) Very High Speed Integrated Circuits (b) Very Higher Speed Integration Circuits (c) Variable High Speed Integrated Circuits (d) Variable Higher Speed Integration Circuits
Transcribed Image Text:Q2/ Choose five only 1-A stage in shift register consist of a) latch b) Flip flop c) Byte of storage 2-a modulus 10-johanson counter requires a) ten flip-flop b) four flip_flop c) five flip_flop 3-A PAL consist of a a) Programmable AND array and programmable OR array b) Programmable AND array and a fixed OR array c) Fixed AND/OR array 4- if an S_R latch has a 1 on the S input and a 0 on the are input and then the input goes to 0 , the latch will be a) set b) RESET c) CLEAR 5-Type of PLD programmable link process technologies are a) EEPROM b) ROM c) antifuse d) both A and C 6-VHSIC stands for (a) Very High Speed Integrated Circuits (b) Very Higher Speed Integration Circuits (c) Variable High Speed Integrated Circuits (d) Variable Higher Speed Integration Circuits
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