Digital Logic and Address Decoding
2. This question is about Digital Logic and Address Decoding
A computer is being designed using a microprocessor with a 16-bit address bus (A0—
A15, where A0 is the least significant bit). The 64K address space is to be split between
and allocated to RAM, ROM and I/O hardware as follows:
Address Range (hex) Contains Select Signal
0x0000 — 0x1FFF Main RAM RAMCS
0x8000 — 0x9FFF Video RAM VRAMCS
0xB000 — 0xBFFF I/O hardware IOCS
0xC000 — 0xCFFF BASIC ROM BROMCS
0xF000 — 0xFFFF OS ROM OSROMCS
The rest of the address space is unused.
Note: As with many computer systems, it its only necessary to decode addresses to
sufficiently identify each of the sections above uniquely. It is acceptable for some parts
to be decodeable by more than one address provided these extra addresses do not
overlap any of the other specified address ranges.
Using a combination of AND, OR and NOT gates and the signals (A12 — A15) that
contain the top four bits of the address in binary form:
a. Derive the equation for a logic signal, RAMCS, which is true if the address bus contains
an address in the range for the Main RAM.
b. Derive the equation for a logic signal, VRAMCS, which is true if the address bus contains
an address in the range for the Video RAM.
c. Derive the equation for a logic signal, IOCS, which is true if the address bus contains an
address in the range for the I/O hardware.
d. Derive the equation for a logic signal, BROMCS, which is true if the address bus contains
an address in the range for the BASIC ROM.
e. Derive the equation for a logic signal, OSROMCS, which is true if the address bus
contains an address in the range for the OS ROM.
f. A second, separate 8K block of RAM is added to the system at addresses 0x2000—
0x2FFF.
i. Derive the equation for a logic signal, RAM2CS, which is true if the address bus
contains an address in the range for the newly added RAM.
ii. Which, if any, of your existing logic equations for RAMCS, VRAMCS, IOCS, BROMCS,
OSROMCS would need to be changed so that they still uniquely decode the
respective areas of memory after the new block of RAM is added.
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