The following assumes the LC-3 architecture. Consider following table that represents several of the 16-bit registers in the register file: Register RO R1 R2 Also consider the following table that represents part of the memory of a 16-bit address space that has an addressability of 2 bytes: ADDRESS (hex) CONTENTS (binary) Ox0321 Ox0320 Ox031F Ox031E ADD JMP LDR Ox021C Ox021B Ox021A REFERENCE: Table of LC-3 Instructions: Assume the PC has the address Ox021C when FETCH INSTRUCTION phase begins. After that first instruction executes, which one desc LDR R4 with a value from memory ADD R4 to R5 and save result in R7 LDR R5 with a value from memory ADD R5 to R6 and save result in R7 15 CONTENTS (binary) 0000 0011 0001 1110 0000 0011 0010 0000 0000 0011 0010 0001 14 13 0 0 0 1 1 1 00 0 1 10 12 0001 1111 0000 0101 0001 1111 0100 0110 0110 1010 1100 0100 0110 1000 1101 0101 1100 0000 0000 0000 1100 0000 1000 0000 1100 0000 0100 0000 11 10 DST 000 DST 7 SRC1 Base Base 6

The following assumes the LC-3 architecture. Consider following table that represents several of the 16-bit registers in the register file: Register RO R1 R2 Also consider the following table that represents part of the memory of a 16-bit address space that has an addressability of 2 bytes: ADDRESS (hex) CONTENTS (binary) Ox0321 Ox0320 Ox031F Ox031E ADD JMP LDR Ox021C Ox021B Ox021A REFERENCE: Table of LC-3 Instructions: Assume the PC has the address Ox021C when FETCH INSTRUCTION phase begins. After that first instruction executes, which one desc LDR R4 with a value from memory ADD R4 to R5 and save result in R7 LDR R5 with a value from memory ADD R5 to R6 and save result in R7 15 CONTENTS (binary) 0000 0011 0001 1110 0000 0011 0010 0000 0000 0011 0010 0001 14 13 0 0 0 1 1 1 00 0 1 10 12 0001 1111 0000 0101 0001 1111 0100 0110 0110 1010 1100 0100 0110 1000 1101 0101 1100 0000 0000 0000 1100 0000 1000 0000 1100 0000 0100 0000 11 10 DST 000 DST 7 SRC1 Base Base 6

Computer Networking: A Top-Down Approach (7th Edition)

7th Edition

ISBN:9780133594140

Author:James Kurose, Keith Ross

Publisher:James Kurose, Keith Ross

Chapter1: Computer Networks And The Internet

Section: Chapter Questions

Problem R1RQ: What is the difference between a host and an end system? List several different types of end...

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Question

The following assumes the LC-3 architecture.
Consider following table that represents several of the 16-bit registers in the register file:
Register
RO
R1
R2
Also consider the following table that represents part of the memory of a 16-bit address space that has an addressability of 2 bytes:
ADDRESS (hex)
CONTENTS (binary)
Ox0321
0x0320
Ox031F
Ox031E
Ox021C
Ox021B
Ox021A
ADD
JMP
LDR
REFERENCE:
Table of LC-3 Instructions:
Assume the PC has the address Ox021C when FETCH INSTRUCTION phase begins. After that first instruction executes, which one describes the second instruction to execute?
LDR R4 with a value from memory
ADD R4 to R5 and save result in R7
LDR R5 with a value from memory
ADD R5 to R6 and save result in R7
15
CONTENTS (binary)
0000 0011 0001 1110
0000 0011 0010 0000
0000 0011 0010 0001
14
13
0 0 0 1
1 1
O 0
0
1
1
0
12
0001 1111 0000 0101
0001 1111 0100 0110
0110 1010 1100 0100
0110 1000 1101 0101
1100 0000 0000 0000
1100 0000 1000 0000
1100 0000 0100 0000
11
10
DST
000
DST
9
8
7
SRC1
Base
Base
6
5
0
4
0
3
0
000 000
Offset
2
1
SRC2
0

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