Hello. I keep getting stuck designing this circuit. Could you help me figure this out? Thank you for your time. ←HW 6 321 (X ✪ Microsoft W X321 Chap 4 Xhttps://docs.google.com/document/d/1jjFN_bnl7Ai8X6_SFfB6fC0YkDvT1hf4po_nyf0HWtE/edit100%Untitled documentFile Edit View Insert Format Tools Extensions Help Last edit was seconds agoType here to search321 Chap 5 XNormal text1ArialMicroelectrox M Inbox (1,240 X-11 + B I U AVTOY20FK'1 COOLEO 23TABLE 4.6MOS Transistor ParametersGNMOS DEVICE+0.75 V0.75√ V0.6 V100 µA/V²4Design a four-resistor bias network for an NMOStransistor to give a Q-point of (500 μA, 5 V) withVDD 12 V and REQ = 600 ks. Use the parame-ters from Table 4.6.5Untitled do XPMOS DEVICE-0.75 V0.5√V39%0.6 V40 μ.A/V2im6.46°FHw#1/#2 SX✓ ✓o!!!7 COLE EAⓇ+3D□XAdd comment53=S ☐ShareEditing4:26 PM11/12/2022XT:

Given,VT0=0.75V,VDD=12V,REQ=600 kΩ,Q-Point ID,VDS=500μA, 5V,K'=μnCox=100 μAV2,γ=0.75 V,2ϕF=0.6V.Threshold Voltage VT is expressed as,VT=VT0+γ2ϕF+VSB-2ϕF,Value of VSB is not given, so VSB will be considered to be 0V.∴VT=VT0+γ2ϕF+0-2ϕF,⇒VT=VT0+0,⇒VT=0.75V. The 4-resistor bias network for the MOSFET is as shown below,Considering saturation state, NMOS current is given as:ID=K'2·WL·VGS-VT2,Let, WL=10,⇒500μ=100μ×102VGS-VT2,⇒500μ=500μVGS-VT2,⇒VGS-VT2=1,⇒VGS-VT=±1,In NMOS, for current to flow, VGS>VT,∴VGS-VT=+1,⇒VGS=0.75+1,⇒VGS=1.75V. Given,REQ=600 kΩ,Let, R1=R2,Now,REQ=R1∥R2,⇒REQ=R1×R2R1+R2,⇒REQ=R1×R1R1+R1, ∵R1=R2,⇒REQ=R122R1,⇒REQ=R12,⇒R1=2×600kΩ,⇒R1=1.2MΩ.∴R1=R2=1.2MΩ.Now, VG=VDD×R2R1+R2,⇒VG=12×1.2M1.2M+1.2M,⇒VG=6V,Now,VDS≥VGS-VT,⇒VDS≥VG-VS-VT,⇒VS≥VG-VDS-VT,⇒VS≥6-5-0.75,⇒VS≥0.25V. Let, VS=1V.Using Ohm's Law,VS=IDRS,⇒IDRS=1,⇒RS=1500μ=1500×10-6,⇒RS=106500,⇒RS=2000,∴RS=2 kΩ.Applying KVL from DC supply to ground through drain and source,-12+IDRD+VDS+IDRS=0,⇒IDRD=12-VDS-IDRS,⇒RD=12-VDS-IDRSID,Substituting all the values in the above equation,RD=12-5-500×10-6×2000500×10-6,⇒RD=6×1065,⇒RD=1.2×106,∴RD=1.2 MΩ. The final circuit is as shown below,