Design a circuit that relates the number of Os and 1s present in 4 inputs A, B, C and D to two outputs, X1 X0 such that if there are at least two consecutive 1s then X1 is 1 and 0 else; if there are at least two consecutive Os then X0 is 1 and 0 otherwise. a) Write the truth table for this circuit and find the minimized logic equations for outputs X¡ in SOP form and Xo in POS form using Karnaugh-maps. b) Draw a gate-level schematic that realizes the function X1 using only 2- input AND, OR gates. Assume that you have all literals. c) Assume that all the gates (AND, OR, NOT) in the previous diagram (part b) have a propagation delay of 100 ps. What is the delay of this circuit? d) literals. Generate the output X1 using 8x1 mux and necessary gates. Assume you have all e) literals. Generate the output X0 using 3x8 decoder and necessary gates. Assume you have all Activate Wi

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Design a circuit that relates the number of Os and 1s present in 4 inputs A, B, C and D to two
outputs, X1 X0 such that if there are at least two consecutive 1s then X1 is 1 and 0 else; if there
are at least two consecutive Os then X0 is 1 and 0 otherwise.
a)
Write the truth table for this circuit and find the minimized logic equations for outputs
Xị in SOP form and Xo in POS form using Karnaugh-maps.
b)
Draw a gate-level schematic that realizes the function X1 using only 2- input AND,
OR gates. Assume that you have all literals.
c)
Assume that all the gates (AND, OR, NOT) in the previous diagram (part b) have a
propagation delay of 100 ps. What is the delay of this circuit?
d)
literals.
Generate the output X1 using 8x1 mux and necessary gates. Assume you have all
Generate the output X0 using 3x8 decoder and necessary gates. Assume you have all
e)
literals.
Activate Wino
Go to Settings to
Transcribed Image Text:Design a circuit that relates the number of Os and 1s present in 4 inputs A, B, C and D to two outputs, X1 X0 such that if there are at least two consecutive 1s then X1 is 1 and 0 else; if there are at least two consecutive Os then X0 is 1 and 0 otherwise. a) Write the truth table for this circuit and find the minimized logic equations for outputs Xị in SOP form and Xo in POS form using Karnaugh-maps. b) Draw a gate-level schematic that realizes the function X1 using only 2- input AND, OR gates. Assume that you have all literals. c) Assume that all the gates (AND, OR, NOT) in the previous diagram (part b) have a propagation delay of 100 ps. What is the delay of this circuit? d) literals. Generate the output X1 using 8x1 mux and necessary gates. Assume you have all Generate the output X0 using 3x8 decoder and necessary gates. Assume you have all e) literals. Activate Wino Go to Settings to
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