Design a 4-bit even parity generator, which has four-bit binary inputs A (A3A2A¡Ao) and produces one output, P. The output P is HIGH (1) if the number of 'l's in the input vector are odd. Output P is LOW if the number of 1's in the input vector are even. Implement this parity generator using a multiplexer IC 74LS151 (8-to-1 multiplexer) as shown in Figure Q2(c). Show all the steps and wiring of the IC 74LS151. (16) (4) 10 (11) so Vcc (3) I1 (2) 12 (10) si (9) S2 (1) 13 (15) 14 (5) (14) 15 (6) (13) 16 (12) 17 (7) EN GND (8) Figure Q2(c) N IN
Design a 4-bit even parity generator, which has four-bit binary inputs A (A3A2A¡Ao) and produces one output, P. The output P is HIGH (1) if the number of 'l's in the input vector are odd. Output P is LOW if the number of 1's in the input vector are even. Implement this parity generator using a multiplexer IC 74LS151 (8-to-1 multiplexer) as shown in Figure Q2(c). Show all the steps and wiring of the IC 74LS151. (16) (4) 10 (11) so Vcc (3) I1 (2) 12 (10) si (9) S2 (1) 13 (15) 14 (5) (14) 15 (6) (13) 16 (12) 17 (7) EN GND (8) Figure Q2(c) N IN
Introductory Circuit Analysis (13th Edition)
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ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
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q2 c
Transcribed Image Text:(c) Design a 4-bit even parity generator, which has four-bit binary inputs A (A3A2A¡Aq) and
produces one output, P. The output P is HIGH (1) if the number of 'l's in the input vector are
odd. Output P is LOW if the number of 1's in the input vector are even. Implement this parity
generator using a multiplexer IC 74LS151 (8-to-1 multiplexer) as shown in Figure Q2(c).
Show all the steps and wiring of the IC 74LS151.
(16)
(4)
I0
Vcc
(11)
SO
(3)
I1
(10)
Si
(2)
12
(9)
S2
(1)
13
(15)
14
(5)
(14)
15
(6)
(13)
16
(12)
17
(7)
EN
GND
(8)
Figure Q2(c)
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