Considering (no+17) = (abcdefg)₂, design a synchronous sequence detector circuit that etects 'abcdefg' from a one-bit serial input stream applied to the input of the circuit with each active clock dge. The sequence detector should detect overlapping sequences. a) Derive the state diagram, describe the meaning of each state clearly. Specify the type of the sequential circuit (Mealy or Moore), b) Determine the number of state variables to use and assign binary codes to the states in the state diagram, c) Choose the type of the FFs for the implementation. Give the complete state table of the sequence detector, using reverse characteristics tables of the corresponding FFs d) Obtain Boolean functions for state inputs. Also obtain the output Boolean expression, e) Draw the corresponding logic circuit for the sequence detector.

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