Consider this state transition process for an FSM with 2 states. Write a truth table for the state signal as a function of the current state and the input x.Write a truth table for the output Y as a function of the current state.Implement the next state logic using a CLB logic slice.

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Consider this state transition process for an FSM with 2 states.

Write a truth table for the state signal as a function of the current state and the input x.Write a truth table for the output Y as a function of the current state.Implement the next state logic using a CLB logic slice. 

state proc: process (clk)
begin
case state is
when STATE1 =>
if x = '1' then
state <= STATE2;
end if;
when STATE2 =>
if x = ¹0 then
state <= STATE1;
end if;
end case;
end process state_proc;
Y <= '1' when state = STATE2 else '0';
Transcribed Image Text:state proc: process (clk) begin case state is when STATE1 => if x = '1' then state <= STATE2; end if; when STATE2 => if x = ¹0 then state <= STATE1; end if; end case; end process state_proc; Y <= '1' when state = STATE2 else '0';
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