Consider the operation of a machine with the data path of the figure below. Let us call this machine "Teletraan-1". Teletraan-1 has no pipeline. Suppose that fetching an instruction takes 4 nsec, decoding an instruction takes 1 nsec, fetching the operands from memory or registers to ALU takes 2 nsec, running the ALU takes 2 nsec, storing the result back to the destination registers takes 1 nsec. How much time does Teletraan-1 need to execute 1 million instructions? A. 1 nsec x 1 million = 0.001 second B. 2 nsec x 1 million = 0.002 second C. 4 nsec x 1 million = 0.004 second D. 10 nsec x 1 million = 0.01 second 2. Since the above machine Teletraan-1 has no pipeline, an instruction must be completed in one CPU clock cycle. As a result, a CPU clock cycle must be longer than or equal to the execution time of one instruction. To improve it, we developed "Teletraan-2". Teletraan-2 has a fivestage pipeline. It takes 5 nsec to fetch an instruction, 2 nsec to decode an instruction, 3 nsec to fetch operands, 3 nsec to execute an instruction in the ALU, and 2 nsec to write data back to the destination registers. In this situation, each stage must be completed in one CPU clock cycle. What is the minimum length of one CPU clock cycle? A. 2 nsec B. 3 nsec C. 5 nsec D. 15 nsec
1. Consider the operation of a machine with the data path of the figure below. Let us call this
machine "Teletraan-1". Teletraan-1 has no pipeline. Suppose that fetching an instruction takes
4 nsec, decoding an instruction takes 1 nsec, fetching the operands from memory or registers
to ALU takes 2 nsec, running the ALU takes 2 nsec, storing the result back to the destination
registers takes 1 nsec.
How much time does Teletraan-1 need to execute 1 million instructions?
A. 1 nsec x 1 million = 0.001 second
B. 2 nsec x 1 million = 0.002 second
C. 4 nsec x 1 million = 0.004 second
D. 10 nsec x 1 million = 0.01 second
2. Since the above machine Teletraan-1 has no pipeline, an instruction must be completed in one
CPU clock cycle. As a result, a CPU clock cycle must be longer than or equal to the execution
time of one instruction. To improve it, we developed "Teletraan-2". Teletraan-2 has a fivestage pipeline. It takes 5 nsec to fetch an instruction, 2 nsec to decode an instruction, 3 nsec to
fetch operands, 3 nsec to execute an instruction in the ALU, and 2 nsec to write data back to
the destination registers. In this situation, each stage must be completed in one CPU clock cycle.
What is the minimum length of one CPU clock cycle?
A. 2 nsec
B. 3 nsec
C. 5 nsec
D. 15 nsec
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