Consider the following assembly code:InstructionDescriptionLD R1, 45(R2)Read data from memory and store in R1. Memory address is calculated by adding 45 to the content of R2ADD R7, R1, R5Add contents of R1 and R5 and store to R7XOR R2, R7, R7Logical Ex-OR between contents of R7 with R7 and store result in R2Jump to Target if R7 is ZeroRead data from memory and store in R3. Memory address is calculated by adding 50 to the content of R4Read data from memory and store in R5. Memory address is calculated by adding 45 to the content of R6BEZ R2, TargetLD R3, 50(R4)LD R5, 45(R6)ADD R10, R5, R3Add contents of R5 to R3 and store in R2Target: AND R2, R3, R5Logical AND between contents of R3 & R5. Store result to R2ADD R10, R8, R2Add contents of R2 and R8 and store to R10ENDUse five-stage pipeline containing Fetch, Decode, Memory read, Execute, Write-back units, show the execution of above instructions. Datadependencies and control hazards, if detected must be resolved by delaying the pipeline as required. Assume that a multi-port RAM is used withthe CPU running at 1GHZ and each section requires 3 clock cycles. Calculate the execution time.

Here, I have to provide a solution to the above question.

Consider the following assembly code: Description Read data from memory and store in R1. Memory address is calculated by adding 45 to the content of R2 Instruction LD R1, 45(R2) ADD R7, R1, R5 Add contents of R1 and R5 and store to R7 XOR R2, R7, R7 Logical Ex-OR between contents of R7 with R7 and store result in R2 BEZ R2, Target LD R3, 50(R4) Jump to Target if R7 is Zero Read data from memory and store in R3. Memory address is calculated by adding 50 to the content of R4 Read data from memory and store in R5. Memory address is calculated by adding 45 to the content of R6 LD R5, 45(R6) ADD R10, R5, R3 Add contents of R5 to R3 and store in R2 Target: AND R2, R3, R5 Logical AND between contents of R3 & R5. Store result to R2 ADD R10, R8, R2 Add contents of R2 and R8 and store to R10 END Use five-stage pipeline containing Fetch, Decode, Memory read, Execute, Write-back units, show the execution of above instructions. Dat dependencies and control hazards, if detected must be resolved by delaying the pipeline as required. Assume that a multi-port RAM is used wit the CPU running at 1GHZ and each section requires 3 clock cycles. Calculate the execution time.

Consider the following assembly code: Description Read data from memory and store in R1. Memory address is calculated by adding 45 to the content of R2 Instruction LD R1, 45(R2) ADD R7, R1, R5 Add contents of R1 and R5 and store to R7 XOR R2, R7, R7 Logical Ex-OR between contents of R7 with R7 and store result in R2 BEZ R2, Target LD R3, 50(R4) Jump to Target if R7 is Zero Read data from memory and store in R3. Memory address is calculated by adding 50 to the content of R4 Read data from memory and store in R5. Memory address is calculated by adding 45 to the content of R6 LD R5, 45(R6) ADD R10, R5, R3 Add contents of R5 to R3 and store in R2 Target: AND R2, R3, R5 Logical AND between contents of R3 & R5. Store result to R2 ADD R10, R8, R2 Add contents of R2 and R8 and store to R10 END Use five-stage pipeline containing Fetch, Decode, Memory read, Execute, Write-back units, show the execution of above instructions. Dat dependencies and control hazards, if detected must be resolved by delaying the pipeline as required. Assume that a multi-port RAM is used wit the CPU running at 1GHZ and each section requires 3 clock cycles. Calculate the execution time.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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