Consider a 64KB cache that uses the following unusual address breakdown: Assume the following code runs on this caching system: int total = 0; int *heapArray = malloc(sizeof(int) * 4096); //int is 4 bytes for (int i = 0; i < 4096; i++) total+heapArray[i]; O 1024 01 0 2 O 512 O 256 32-bit Address Breakdown bit 31 04 24 What is the maximum number of memory blocks for the array that are stored in the cache at any point in time? s bits 16 t bits 8 b bits

Consider a 64KB cache that uses the following unusual address breakdown: Assume the following code runs on this caching system: int total = 0; int heapArray = malloc(sizeof(int) 4096); //int is 4 bytes for (int i = 0; i < 4096; i++) total+heapArray[i]; O 1024 01 0 2 O 512 O 256 32-bit Address Breakdown bit 31 04 24 What is the maximum number of memory blocks for the array that are stored in the cache at any point in time? s bits 16 t bits 8 b bits

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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c) The table below represents 10 lines from a 256 line cache that uses direct mapping with a block size of 4 words. Identify the address of the shaded data (8C16). 3 Line# Tag Word 10 Word 11 Word Word 00 01 110101 12 34 56 78 1 010101 54 32 6A D3 2 000111 8C A2 BC 29 ED F3 001100 33 20 C8 FO 110011 9A D8
A byte offset of 2 in an address means that each set in a multiway set associative (or in the directly mapped) cache has 4 bytes per set, per cache line. Keeping this in mind, answer the questions given the following details. A cache is organized as a 4 way set associative cache Each set's cache line consists of 4 words (meaning there are 16 bytes per line, for each set of the cache). Each set individually has one Valid bit, and one Dirty bit, for each line. The tag field of this cache is 8 bits wide. The address is 32 bits wide. Question 1g) If we have a write through cache coherency policy, will either of the above organizations make a difference in the amount of power used to do one write through operation (specifically above this cache layer, in the upper level memory structures to maintain coherency.
Suppose we have a byte-addressable computer with a cache that holds 8 blocks of 16 bytes each. Assuming that each memory address has 16 bits, to which cache block would the hexadecimal address 0x13F map if the computer uses direct mapping? Blocks are numbered starting at 0.
Suppose we have a byte-addressable computer with a cache that holds 8 blocks of 4 bytes each. Assuming that each memory address has 8 bits, to which cache block would the hexadecimal address 0x2D map if the computer uses direct mapping? Blocks are numbered starting at 0
For a direct-mapped cache with 64KİB data, 8-word blocks, and 32-bit addresses, answer the following questions: a) What is the number of blocks/lines in the cache? b) Identify the bits in the 32-bit address that are used as index bits? c) Identify the bits in the 32-bit address that are used as tag bits? d) What is the total number of bits in this cache (including tag field and valid field)? e) Identify the block number in the cache to which the following 32-bit memory address maps: Ox00003Z00 (Hexadecimal notation) where Z is the least significant digit in your student ID (written as a decimal number)
3. The table below represents five lines from a cache that uses fully associative mapping with a block size of 8. Identify the address of the shaded data, 0xE6, first in binary and then in hexadecimal. The tag numbers and word id bits are in binary, but the content of the cache (the data) is in hexadecimal. Word id bits Tag 000 001 010 011 100 101 110 111 ------------------------------------------ 1011010 10 65 BA 0F C4 19 6E C3 1100101 21 76 CB 80 D5 2A 7F B5 0011011 32 87 DC 91 E6 3B F0 A6 1100000 43 98 ED A2 F7 4C E1 97 1111100 54 9A FE B3 08 5D D2 88
Consider a cache with 32KİB data, 16-word blocks, and 24-bit addresses, answer the following questions: a) For the direct-mapped configuration, determine the number of index bits and tag bits in the 24-bit address. b) For 4-way set associative configuration, determine the number of index bits and tag bits in the 24-bit address. c) For fully associative contiguration, determine the number of index bits and tag bits in the 24-bit address. d) For an 8-way set associative configuration, identify the set number in the cache to which the following 24-bit memory address maps: Ox001Z00 (Hexadecimal notation) where Z is the least significant digit in your student ID (written as a decimal number)
Explain the reasons why it is so difficult to devise a suitable cache replacement technique that works for all address sequences.
Question 23 Some portion of cache system A represented below. The system is byte-addressable and the block size is one word (4 bytes). The tag and line number are represented with a binary numbers. The contents of words in the block are represented with hexadecimal. Tag 10 1000 0100 1001 10 1000 0100 1001 10 1000 0100 1001 10 1000 0100 1101 Line Number 0110 1101 0110 1110 0110 1111 B1 FF B8 A1 FF B8 B1 FF B8 A1 FF B8 B1 FF B8 0111 0000 1. What is the size of the main memory of this system? 2. What is the size of the cache memory of this system? 00 Word within block 2016 6116 C116 2116 01 10 11 3216 7216 C216 D216 4216 8216 4116 A216 E216 9216 5216 B216 3. If the CPU requests to read memory address A1 25 BA, what data does the CPU receive? 4. If the CPU requests to read memory address A1 35 C2, what data does the CPU receive? 5. If we access memory in the following order in cache system A: A1 FF B8 how many cache misses would occur for the data request?
Assume that you have a direct-mapped cache with 16 indices and each block can contain 32 words. Assuming that each bytes address is 32 bits long (and a word is 32 bits), answer the following questions: a). How many bits in each address are used for its tag? bits b). Compute the total number of bits required to implement this cache, including valid bits, tag bits and bits used for data. bits
Consider a 32-bit physical memory space and a 32 KiB 2-way associative cache with LRU replacement. You are told the cache uses 5 bits for the offset field. Write in the number of bits in the tag and index fields. Tag length in bits = Index length in bits =
c) The table below represents 5 lines from a 256 line cache that uses direct mapping with a block size of 4 words. Identify the address of the shaded data (F316). Word 10 Line# Tag Word Word 11 Word 00 01 110101 12 34 56 78 010101 54 32 6A D3 000111 29 8C ED F3 001100 33 A2 20 C8 4 110011 9A BC D8 FO