Choose the best answer that completes the statement or answers the question. 1- One example of the use of an S-R flip-flop is as a)Transition pulse generator b) Racer e) Switch debouncer d) Astable oscillator 2-Which of the following is correct for a gated D-type flip-flop? a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW b) The output complement follows the input when enabled c) Only one of the inputs can be HIGH at a time d) The output toggles if one of the inputs is held HIGH 3-How is a J-K flip-flop made to toggle? a) J = 0, K = 0 b)J =1, K = 0 c)J = 0, K =1 d) J = 1, K = 1

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Choose the best answer that completes the statement or answers the question.
1- One example of the use of an S-R flip-flop is as
a)Transition pulse generator b) Racer c) Switch debouncer d) Astable oscillator
2-Which of the following is correct for a gated D-type flip-flop?
a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH
3-How is a J-K flip-flop made to toggle?
a) J = 0, K = 0 b) J= 1, K = 0 c) J = 0, K = 1
d) J = 1, K = 1
4- A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input, The Q output is
a) Constantly LOW b) Constantly HIGH c) A 20 kHz square wave d) A 10 kHz square wave
5-Determine the output frequeney for a frequency division circuit that contains 12 flip-flops
with an input clock frequeney of 20.48 MHz.
a) 10.24 kHz b) 5 kHz c)30.24 kHz d) 15 kHz
6- A positive edge-triggered D flip-flop will store a 1 when
a) The D input is HIGH and the clock transitions from HIGH to Low
b) The D input is HIGH and the clock transitions from LOW to HIGH
c) The D input is HIGH and the clock is LOW
d) The D input is HIGH and the clock is HIGH
7- A counter circuit is usually constructed of_
a) A number of latches connected in cascade form
b) A number of NAND gates connected in cascade form
c) A number of flip-flops connected in cascade
d) A number of NOR gates connected in cascade form
Transcribed Image Text:Choose the best answer that completes the statement or answers the question. 1- One example of the use of an S-R flip-flop is as a)Transition pulse generator b) Racer c) Switch debouncer d) Astable oscillator 2-Which of the following is correct for a gated D-type flip-flop? a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW b) The output complement follows the input when enabled c) Only one of the inputs can be HIGH at a time d) The output toggles if one of the inputs is held HIGH 3-How is a J-K flip-flop made to toggle? a) J = 0, K = 0 b) J= 1, K = 0 c) J = 0, K = 1 d) J = 1, K = 1 4- A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input, The Q output is a) Constantly LOW b) Constantly HIGH c) A 20 kHz square wave d) A 10 kHz square wave 5-Determine the output frequeney for a frequency division circuit that contains 12 flip-flops with an input clock frequeney of 20.48 MHz. a) 10.24 kHz b) 5 kHz c)30.24 kHz d) 15 kHz 6- A positive edge-triggered D flip-flop will store a 1 when a) The D input is HIGH and the clock transitions from HIGH to Low b) The D input is HIGH and the clock transitions from LOW to HIGH c) The D input is HIGH and the clock is LOW d) The D input is HIGH and the clock is HIGH 7- A counter circuit is usually constructed of_ a) A number of latches connected in cascade form b) A number of NAND gates connected in cascade form c) A number of flip-flops connected in cascade d) A number of NOR gates connected in cascade form
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