Please answer only the letter (c). Thank you Assignment 1: A RISC processor that uses the five-stage instruction fetch and execution designintroduced in Chapter 5 is driven by a 3-GHz clock. Instruction statistics in a large program are asfollows:Branch10%Load40%Store30%Arithmetic and logic instructions20%Assume all the instructions need these five stages to complete, and there is no pipelined execution.Please answer the following questions.(a) Assume the memory access operation is always completed in one clock cycle. What will be therate of instruction execution (ie average number of instructions executed per second)?(b) Assume the memory access operation is always completed in one clock cycle. What is thefrequency of memory access operations (ie average number of memory access operations per second)when the program is executed?(c) Assume 80% of instruction fetch operations are completed in one clock cycle and 20% arecompleted in 4 clock cycles. In addition, on average, the memory stage of a Load or Store instructionis completed in 3 clock cycles. What will be the rate of instruction execution (ie average number ofinstructions executed per second)?

Name: Please answer only the letter (c). Thank you Assignment 1: A RISC proc
Uploaded: 2024-03-20T06:51:23.000Z
Channel: Bartleby
Description: Please answer only the letter (c). Thank you Assignment 1: A RISC processor that uses the five-stage instruction fetch and execution designintroduced in Chapter 5 is driven by a 3-GHz clock. Instruction statistics in a large program are asfollows:Bra