b) A feedback control system is shown in Fig. 3. + R(s)- S+1 K → Y(s) s(s + 2)(s+3) i.. ii. iii. 1V. V. (5²+25)(5+5) 5+352 +252 +65 স 55 3² + 55² +65 Fig. 3 Plot the pole(s) and zero(s) of the system on the s-plane. 5/3²+35+ 5 +35 3 2 + Calculate and sketch the centroid and the asymptotic line(s). Determine the breakaway/in point (s). Find the imaginary axis crossing point(s). Justify your answer. Sketch and refine the root locus of the system.

Only f,g

Q1) In the DAC circuit below, Rf 10 km2, R1=20 kn find R2, R3, R4 and the analog output voltage for the digital inputs [0000] ... [1111]. Consider Vref= 10 V. V www V₂ V3 V4 R₁ R₂ MSB R3 www RA LSB 41₁ R₁ V

please just answer part e

Which differential equation models a series circuit with impressed voltage and no resistance? O Q" + 60' +180 = 0 3Q" + 18Q = 0 O Q" + 1400' + 5100Q = 20sin (17nt) 250" + 100Q = 10cos (5nt)

please just answer part d

By hand Solution needed Neat and clean solution required in the order to get positive feedback please show me neat and clean solution required it Both parts needed to be done correctly

can you help me please? The DC inputs of the ideal opamp circuit given in the figure are respectively V1=3V and V2 =9V. Calculate the output V0 of this circuit.

Q4 Briefly discuss the importance of A/D and D/A converters for the case of digital control. Also, draw a detailed block diagram to show where a digital computer can be placed in the control loop. (a) (b) Consider the open-loop system as shown in Figure Q4. T Y(s) ZOH G,(s) R(s) U(s) Figure Q4 The plant is described as: * = (, )x + (;)u y = [1 0]x (i) Find the transfer function of the plant, Gp(s). Note, that the transfer function Y(s) can be defined as, Y(s) = C(sl – A)-'B + D where A, B, C, D and I are state, input, output, feedforward and identity matrix respectively. Find the sampled-data transfer function G(z). Assume a sample period of T, and the transfer function of the ZOH as (1-eT/s. (ii) rane (iii) Find the sampled-data transfer function, G(z), for T= 0.5 s. (iv) Explain why it is not practical to make sample time too low to reduce the effective delay of sample and hold. Note, that the effective delay of sample and hold is typically half of the sample time.

Please explain the step as I mark in picture