Assume that we have a simple processor which is able to execute 7 instructions: load (ld), store double world (sd), add (add), subtract (sub), AND (and), OR (or), and br (beq). Assume the operation times for the major functional units are in the table (as address for beq instructions is calculated by ALU): Inst. Fetch Reg. Read Data Mem. ALU Operation 200ps 200ps 100ps 200ps a) If the processor is in single-cycle model, what are total times for load double store doubleword (sd), R-format (add, sub, and, or), and branch if equal (be instructions, respectively? What is the (minimum) clock period? b) If the processor is 5-stage pipelined (with steps Inst. Fetch, Reg. Read, ALU Data Mem., and Reg. Write), what is the (minimum) clock period? What is 1/11 Reg. 100

Assume that we have a simple processor which is able to execute 7 instructions: load (ld), store double world (sd), add (add), subtract (sub), AND (and), OR (or), and br (beq). Assume the operation times for the major functional units are in the table (as address for beq instructions is calculated by ALU): Inst. Fetch Reg. Read Data Mem. ALU Operation 200ps 200ps 100ps 200ps a) If the processor is in single-cycle model, what are total times for load double store doubleword (sd), R-format (add, sub, and, or), and branch if equal (be instructions, respectively? What is the (minimum) clock period? b) If the processor is 5-stage pipelined (with steps Inst. Fetch, Reg. Read, ALU Data Mem., and Reg. Write), what is the (minimum) clock period? What is 1/11 Reg. 100

Computer Networking: A Top-Down Approach (7th Edition)

7th Edition

ISBN:9780133594140

Author:James Kurose, Keith Ross

Publisher:James Kurose, Keith Ross

Chapter1: Computer Networks And The Internet

Section: Chapter Questions

Problem R1RQ: What is the difference between a host and an end system? List several different types of end...

See similar textbooks

Similar questions

In generall, computers think in terms of numbers (i.e. binary data). Thus, any operation performed in the computer must be done using either mathematical or logical operations. Given this inherit limitation of computers, what is the compare instruction actually doing when we, as assembly programmers, provide two numbers for it to "compare"? Furthermore, what assembly instruction is similar to the compare instruction? How are the two instructions different?
Stack Pointer OF28H 1234h 3358h STACK Show the content of the stack, the content of STKPTR register and TOS registers (TOSU, TOSH, and TOSL) after the execution of following instruction: Address Ох0284 Content РОP
Convert the given hex value to its R-format MIPS instruction by completing the following table. The instruction and letters for registers must be in lower case. DO NOT TYPE DOLLAR SIGNS WITH REGISTERS. Hex Opcode (decimal) rs (decimal) rt (decimal) rd (decimal) funct (decimal) Instruction 02488822 O 18 16 17 34 sub s4 $$1 " $ to " LA
Assume a 5-stage pipelined CPU (IF – ID – MU- EX – WR) requires following time for different sections: Required time 15 ns Pipeline stages Fetch Unit Decode Unit 10 ns 20 ns Memory Unit Execution Unit 8 ns 15 ns Write back Unit The maximum delay required to transfer contents from one state to another is 2ns. a) Show the time steps of pipelining stages for the first 10 instructions of a program. Assume that Instruction-4 is a conditional loop instruction. If the condition is TRUE, CPU runs instructions: 7 - 9 twice. Please note that a single-port RAM is used with the system, such that CPU read only one data from RAM or save only one data to RAM at a time. Calculate the execution time for the first 10 instructions of a program as well. b) Show the time steps and calculate the execution time for above problem while a multiport RAM is used with the system.
The stack segment, data segment, and code segment are all separate entities. Next, ascertain which combination of registers is used to address data items inside each segment.
18 What is speculation as it relates to parallelization? It is the set of instructions that issues together in one clock cycle and the packet may be determined statically by the compiler or dynamically by the processor. It is a style of instruction set architecture that launches many operations that are defined to be independent in a single wide instruction, typically with many separate opcode fields. It is the number of clock cycles between a load instruction and an instruction that can use the result of the load without stalling the pipeline. O It is an approach whereby the compiler or processor guesses the outcome of an instruction to remove it as a dependence in executing other instructions.
microprocessor