Assume that the Multi-Cycle CPU discussed in the class is updated to support various new RSIC-V instructions. This caused: • The finite state machine of the main control unit contains 18 states and o Increased the number of control signals to 20 bits. Answer the following questions assuming that the updated main control unit is implemented using two ROMS (Le. NSL ROM and OFL ROM): PCWrite Branch lorD MemRead MemWrite IRWrite MemToReg 212x17 ALUOp ALUSrcB ROM ALUSecA Control Logic RegWrite NS3 NS2 NSI NSO Address Opcode State Register I The size of the Output Function Logic (OFL) ROM is: O 25 x 13 bits O 24 x 13 bits O 24 x 20 bits O 25 x 25 bits O 25 x 20 bits O 24x 25 bits JThe width of each location in the Next State Logic (NSL) ROM is: O 20 bits O 4 bits O 25 bits O 17 bits O 5 bits

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Assume that the Multi-Cycle CPU discussed in the class is updated to support various new
RSIC-V instructions.
This caused:
• The finite state machine of the main control unit contains 18 states and
o Increased the number of control signals to 20 bits.
Answer the following questions assuming that the updated main control unit is implemented
using two ROMS (i.e. NSL ROM and OFL ROM):
PCWrite
Beanch
TorD
MemRead
MemWrite
IRWrite
MemToReg
ALUO
212x17
ROM
ALUSecB
Control Logic
ALUSecA
RegWrite
NS3
NS2
NSI
NSO
Address
Орсode
State
Register
The size of the Output Function Logic (OFL) ROM is:
O 25 x 13 bits
O 24 x 13 bits
O 24 x 20 bits
O 25 x 25 bits
O 25 x 20 bits
O 24 x 25 bits
| The width of each location in the Next State Logic (NSL) ROM is:
O 20 bits
O 4 bits
O 25 bits
O 17 bits
O 5 bits
Transcribed Image Text:Assume that the Multi-Cycle CPU discussed in the class is updated to support various new RSIC-V instructions. This caused: • The finite state machine of the main control unit contains 18 states and o Increased the number of control signals to 20 bits. Answer the following questions assuming that the updated main control unit is implemented using two ROMS (i.e. NSL ROM and OFL ROM): PCWrite Beanch TorD MemRead MemWrite IRWrite MemToReg ALUO 212x17 ROM ALUSecB Control Logic ALUSecA RegWrite NS3 NS2 NSI NSO Address Орсode State Register The size of the Output Function Logic (OFL) ROM is: O 25 x 13 bits O 24 x 13 bits O 24 x 20 bits O 25 x 25 bits O 25 x 20 bits O 24 x 25 bits | The width of each location in the Next State Logic (NSL) ROM is: O 20 bits O 4 bits O 25 bits O 17 bits O 5 bits
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