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Assume that the MIPS stages have these latencies (in

Assume that the MIPS stages have these latencies (in

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Question 1. Assume that the MIPS stages have these latencies (in ps): Execute Register Read Register Write (EX) Instruction Memory (IF) 50 (ID) 20 30 Suppose that we modified the pipelined processor described in Question 1 such that all data memory reads and memory writes were split into two separate stages of 50 ps. each. a) Would the overall throughput increase or decrease in the modified architecture? b) What is the cycle time of modified pipelined processor? c) What would the resulting speedup be? Data Memory (MEM) 100 (WB) 20
Transcribed Image Text:Question 1. Assume that the MIPS stages have these latencies (in ps): Execute Register Read Register Write (EX) Instruction Memory (IF) 50 (ID) 20 30 Suppose that we modified the pipelined processor described in Question 1 such that all data memory reads and memory writes were split into two separate stages of 50 ps. each. a) Would the overall throughput increase or decrease in the modified architecture? b) What is the cycle time of modified pipelined processor? c) What would the resulting speedup be? Data Memory (MEM) 100 (WB) 20
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