Assume a cache of 32 Kbytes organized as 4 K lines of 8 bytes each. The main memory is 32 MB organized logically as 8 M blocks of 16 bytes each. Determine how to split the address (s-r, r, w) for direct mapping. Determine how to split the address (s, w) for associative mapping. Determine how to split the address (s-d, d, w) for set associative mapping. Assume each cache set is 2 lines of cache.

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Assume a cache of 32 Kbytes organized as 4 K lines of 8 bytes each. The main memory is 32 MB organized logically as 8 M blocks of 16 bytes each.

    • Determine how to split the address (s-r, r, w) for direct mapping.
    • Determine how to split the address (s, w) for associative mapping.
    • Determine how to split the address (s-d, d, w) for set associative mapping. Assume each cache set is 2 lines of cache.

 

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