Fetch and decode Instruction Boolean condition RTL name Fetch TO)L: AR<--PC, SC<-- 0 TI)L: IR<.- M[AR].PC<-PC+1 (DO:D7) <--IR(12:14), I<-- IR(15), AR<-- IR(0:11) row Decode T2)L: hight-30 Indirect D7 L.T3)L: AR<--M[AR] Input/output instructions Instruction Hexadecimal Boolean condition RTL INP F800 (D7.I.T3.IR(11))L: AC(0:7) <-- INPR, OUT <-- AC(0:7), SC <-- 0 (FGI)L:PC <-- PC+1,SC <-- 0 (FGO)L:PC <-- PC+1,SC <-- 0 IEN <--1, SC<- o OUT F400 (D7.L.T3.IR(10))L: SKI F200 (D7.L.T3.IR(9))L: SKO F100 (D7.L.T3.IR(8))L: ION FO80 (D7.LT3.IR(7))L: IOF F040 (D7.L.T3.IR(6))L: IEN < 0, SC<. 0
Fetch and decode Instruction Boolean condition RTL name Fetch TO)L: AR<--PC, SC<-- 0 TI)L: IR<.- M[AR].PC<-PC+1 (DO:D7) <--IR(12:14), I<-- IR(15), AR<-- IR(0:11) row Decode T2)L: hight-30 Indirect D7 L.T3)L: AR<--M[AR] Input/output instructions Instruction Hexadecimal Boolean condition RTL INP F800 (D7.I.T3.IR(11))L: AC(0:7) <-- INPR, OUT <-- AC(0:7), SC <-- 0 (FGI)L:PC <-- PC+1,SC <-- 0 (FGO)L:PC <-- PC+1,SC <-- 0 IEN <--1, SC<- o OUT F400 (D7.L.T3.IR(10))L: SKI F200 (D7.L.T3.IR(9))L: SKO F100 (D7.L.T3.IR(8))L: ION FO80 (D7.LT3.IR(7))L: IOF F040 (D7.L.T3.IR(6))L: IEN < 0, SC<. 0
Chapter4: More Object Concepts
Section: Chapter Questions
Problem 13RQ
Related questions
Question
![column width=15
Appendix A
Fetch and decode
column width=26
column=10 column width=15
column width=26
Instruction
Boolean condition
RTL
name
Fetch
TO)L:
AR<--PC, SC<-- 0
TI)L:
IR<-- M[AR].PC<--PC+1
(DO:D7) <--IR(12:14), I<-- IR(15),
row
Decode
T2)L:
AR<-- IR(0:11)
hight-30
Indirect
D7'.LT3)L:
AR<--M[AR]
Input/output instructions
Instruction Hexadecimal Boolean condition
RTL
INP
F800
(D7.I.T3.IR(11))L:
AC(0:7) <-. INPR,
OUT
F400
(D7.I.T3.IR(10))L:
OUT <-- AC(0:7), SC <-- 0
SKI
F200
(D7.I.T3.IR(9))L:
(FGI)L:PC <-- PC+1,SC <-- 0
SKO
F100
(D7.1.T3.IR(8))L:
(FGO)L:PC <- PC+1,SC <-- 0
ION
FO80
(D7.1.T3.IR(7))L:
IEN <-- 1, SC<.. 0
IOF
F040
(D7.I.T3.IR(6)L:
IEN <.. 0, SC<.. 0
Register reference instructions
Instruction
Memory reference instructions
Hexdecimal Boolean condition
Instruction Hexadecimal
Boolean condition
RTL
RTL
CLA
7800
D7.1.T3.IR(11))L:
AC <-- (0000), SC <-- 0
AND
(0, 8)ххх
DO.T4)L:
DR <-- M[AR]
CLE
7400
(D7.1.T3.IR(10))L:
E <-- (0), SC <.-0
DO.TS)L:
AC <-- (AC.DR)L, SC <-- 0
CMA
7200
(D7.1.T3.IR(9))L:
AC <-- AC', SC <-- 0
ADD
(1,9)ххх
DI.T4)L:
DR <-- M[AR]
СМЕ
7100
(D7.1'.T3.IR(8))L
E <--
E',SC <--0
DI.T5)L:
AC <--(AC+DR), SC <-- 0
CIR
7080
(D7.1.T3.IR(7))L:
AC(14:0) <.. AC(15:1),
AC(15) <-- E,E <-- AC(0). SC <--
LDA
(2, A)xxx
D2.T4)L:
DR <-- M[AR]
CIL
7040
(D7.1.T3.IR(6))L:
AC(15:1) <-- AC(14:0),
D2.T5)L:
AC <-- DR, SC <-- 0
AC(0) <.- E, E <.- AC(15), SC <. 0
INC
7020
(D7.1.T3.IR(5))L:
AC <-- AC+1, SC <-- 0
STA
(3. В)ххх
D3.T4)L:
M[AR] <-- AC, SC <-- 0
SPA
7010
(D7.1.T3.IR(4)L: (AC(15)")L:PC <-- PC+1,
SC <.-
BUN
(4, С)ххх
D4.T4 )L:
PC <--
AR, SC <-- 0
(D7.1'.T3.IR(3))L: (AC(15))L:PC <-- PC+1, SC <-- 0
SNA
7008
SZA
7004
(D7.r.T3.IR(2))L:: (AC=(0000))L:PC <.. PC+1, SC <.- (
BSA
(5, D)xx
DS.T4)L:
M[AR] <-- PC, AR <-- AR+1
DS.T5)L:
PC <-- AR, SC <-- 0
SZE
7002
(D7.1.T3.IR(1))L: (E=0)L:PC <-- PC+1,
SC <-- 0
ISZ
(6, E)xxx
D6.T4)L:
DR <.. M[AR]
HALT
7001
(D7.I.T3.IR(0))L:
S <-- 0, SC <-- 0
D6.T5)L:
DR <-- DR+1
M[AR]<-- DR, SC <-- 0,
(DR=0000)L:PC<-- PC+1)
row hight=30
D6.T6)L:](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Fc9f48e4f-ff71-411c-b008-0b5a34360e93%2Ffd667700-c89e-4916-b541-413e76d625eb%2Fds80h5a_processed.jpeg&w=3840&q=75)
Transcribed Image Text:column width=15
Appendix A
Fetch and decode
column width=26
column=10 column width=15
column width=26
Instruction
Boolean condition
RTL
name
Fetch
TO)L:
AR<--PC, SC<-- 0
TI)L:
IR<-- M[AR].PC<--PC+1
(DO:D7) <--IR(12:14), I<-- IR(15),
row
Decode
T2)L:
AR<-- IR(0:11)
hight-30
Indirect
D7'.LT3)L:
AR<--M[AR]
Input/output instructions
Instruction Hexadecimal Boolean condition
RTL
INP
F800
(D7.I.T3.IR(11))L:
AC(0:7) <-. INPR,
OUT
F400
(D7.I.T3.IR(10))L:
OUT <-- AC(0:7), SC <-- 0
SKI
F200
(D7.I.T3.IR(9))L:
(FGI)L:PC <-- PC+1,SC <-- 0
SKO
F100
(D7.1.T3.IR(8))L:
(FGO)L:PC <- PC+1,SC <-- 0
ION
FO80
(D7.1.T3.IR(7))L:
IEN <-- 1, SC<.. 0
IOF
F040
(D7.I.T3.IR(6)L:
IEN <.. 0, SC<.. 0
Register reference instructions
Instruction
Memory reference instructions
Hexdecimal Boolean condition
Instruction Hexadecimal
Boolean condition
RTL
RTL
CLA
7800
D7.1.T3.IR(11))L:
AC <-- (0000), SC <-- 0
AND
(0, 8)ххх
DO.T4)L:
DR <-- M[AR]
CLE
7400
(D7.1.T3.IR(10))L:
E <-- (0), SC <.-0
DO.TS)L:
AC <-- (AC.DR)L, SC <-- 0
CMA
7200
(D7.1.T3.IR(9))L:
AC <-- AC', SC <-- 0
ADD
(1,9)ххх
DI.T4)L:
DR <-- M[AR]
СМЕ
7100
(D7.1'.T3.IR(8))L
E <--
E',SC <--0
DI.T5)L:
AC <--(AC+DR), SC <-- 0
CIR
7080
(D7.1.T3.IR(7))L:
AC(14:0) <.. AC(15:1),
AC(15) <-- E,E <-- AC(0). SC <--
LDA
(2, A)xxx
D2.T4)L:
DR <-- M[AR]
CIL
7040
(D7.1.T3.IR(6))L:
AC(15:1) <-- AC(14:0),
D2.T5)L:
AC <-- DR, SC <-- 0
AC(0) <.- E, E <.- AC(15), SC <. 0
INC
7020
(D7.1.T3.IR(5))L:
AC <-- AC+1, SC <-- 0
STA
(3. В)ххх
D3.T4)L:
M[AR] <-- AC, SC <-- 0
SPA
7010
(D7.1.T3.IR(4)L: (AC(15)")L:PC <-- PC+1,
SC <.-
BUN
(4, С)ххх
D4.T4 )L:
PC <--
AR, SC <-- 0
(D7.1'.T3.IR(3))L: (AC(15))L:PC <-- PC+1, SC <-- 0
SNA
7008
SZA
7004
(D7.r.T3.IR(2))L:: (AC=(0000))L:PC <.. PC+1, SC <.- (
BSA
(5, D)xx
DS.T4)L:
M[AR] <-- PC, AR <-- AR+1
DS.T5)L:
PC <-- AR, SC <-- 0
SZE
7002
(D7.1.T3.IR(1))L: (E=0)L:PC <-- PC+1,
SC <-- 0
ISZ
(6, E)xxx
D6.T4)L:
DR <.. M[AR]
HALT
7001
(D7.I.T3.IR(0))L:
S <-- 0, SC <-- 0
D6.T5)L:
DR <-- DR+1
M[AR]<-- DR, SC <-- 0,
(DR=0000)L:PC<-- PC+1)
row hight=30
D6.T6)L:
![The initial contents of the basic computer registers and memory are shown below. The table show the instruction fetching stage. You may use the tables in AppendixA.
Complete the highlighted cells in Table.1
Table.1 Basic computer register contents (all values are in hexadecimal
Control condition Register Transfer
D7 E
AC
DR
IR
PC
AR
M[AR]
000 195C,
000 195C,
000 195C,
294C,
200,
Initial Values
Initial Values
1041,
430,
1227
294C,
1041,
430,
31C,
8960,
TO:
AR<--- PC
294C,
1041,
430,
430,
7200,
T1:
IR<--- M[AR), PC <--- PC+1
T2:
AR<--- IR(0-11), I<---IR(15),D0:D7<---IR(14:12)
column width=16
column width=40
To set column width go the top row above rowl click the right mouse on column and set column width to see all the content of the column](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Fc9f48e4f-ff71-411c-b008-0b5a34360e93%2Ffd667700-c89e-4916-b541-413e76d625eb%2Focbn1vc_processed.jpeg&w=3840&q=75)
Transcribed Image Text:The initial contents of the basic computer registers and memory are shown below. The table show the instruction fetching stage. You may use the tables in AppendixA.
Complete the highlighted cells in Table.1
Table.1 Basic computer register contents (all values are in hexadecimal
Control condition Register Transfer
D7 E
AC
DR
IR
PC
AR
M[AR]
000 195C,
000 195C,
000 195C,
294C,
200,
Initial Values
Initial Values
1041,
430,
1227
294C,
1041,
430,
31C,
8960,
TO:
AR<--- PC
294C,
1041,
430,
430,
7200,
T1:
IR<--- M[AR), PC <--- PC+1
T2:
AR<--- IR(0-11), I<---IR(15),D0:D7<---IR(14:12)
column width=16
column width=40
To set column width go the top row above rowl click the right mouse on column and set column width to see all the content of the column
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