Answer the following questions, then describe the function of the circuit: If the input is the equivalent binary number of the decimal 7 what is the output? If the input is the equivalent binary number of the decimal 11 what is the output? ADDER AO Al A2 INO IN 1 IN2 IN3 P3 2222 PO A3 BO P2 Bl PQ CIN Q1

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Design the following combinational logic circuit with a four-bit input and a three-bit output. The input represents two unsigned 2-bit numbers: A1 A0 and B1 B0. The output C2 C1.C0 is the result of the integer binary division A1 A0/B1 B0 rounded down to three bits. The 3-bit output has a 2-bit unsigned whole part C2 C1 and a fraction part CO. The weight of the fraction bit CO is 21. Note the quotient should be rounded down, i.e. the division 01/11 should give the outputs 00.0 (1/3 rounded down to 0) not 00.1 (1/3 rounded up to 0.5). A result of infinity should be represented as 11.1. A minimal logic implementation is not required. (Hint: start by producing a truth table of your design).

(b) Using a synchronous binary counter as shown in Figure Q2(b), design and draw a counter to generate the following repeating sequences 2 to 14 repeatedly for a free running clock. If the circuit happens to enter any of the states 15 or 0 or 1, what are the next states of your circuit? A A Syn. Binary Counter Q3 Q2 Q₁ Qo →Asyn. clear Syn. load CLK D3 D₂ D₁ Do ↑↑↑↑

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This Question is from Digital Logic Design Q1. Assume your register number EF20BCE039 is in Hexadecimal, where014 are the three digits of your registration number.a) Represent your registration number in the binary.b) Split the ten digits of your registration into two Hexadecimal numbers M and N, where the leftmost five digits make number M and the right most five digits make number N. Using r’scomplement, subtract N from M. In other words, calculate M – N.

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Design a combinational circuit that takes 3-bit pattern as input and outputs binary code of bit position of the first 1' in the pattern reading from MSB (2nd position) to LSB (0th position).An additional output variable V is required along with binary code to indicate that the binary code is valid or note i.e., if the input pattern is '000' then the output V should be '0' to indicate that the binary code is not indicating the bit position of first 1' and we don't care about the binary code if V = 0. Design the required circuit using dual 4x1 MUXS and minimum additional logic.Available resources along with dual 4x1 MUXS are NOT gates, 2-input(AND, OR, NAND, NOR) gates.

H.W :- 1) A four logic-signal A,B,C,D are being used to represent a 4-bit binary number with A as the LSB and D as the MSB. The binary inputs are fed to a logic circuit that produces a logic 1 (HIGH) output only when the binary number is greater than 01102-610. Design this circuit. 2) repeat problem 1 for the output will be 0 (LOW) when the binary input is less than 01112-710- Saleem Lateef

Design a logic circuit for decoder that accepts 3-bit input and displays alphabet “048” at the seven- segment as illustrated at Figure 1 (a). The input-output mapping shown in Table 1 (a). Refer Figure 1(b) and Figure 1(c) for seven-segment display format showing arrangements of segments using common anode connection. Show each steps clearly to produce the expressions and required design. [Rekabentuk litar logik untuk penyahkod yang menerima input 3-bit dan paparkan abjad "048" di tujuh-segmen seperti digambarkan pada Rajah 1(a). Pemetaan masukan-keluaran ditunjukkan dalam Jadual 1(a). Rujuk Rajah 1(b) and Rajah 1(c) untuk format paparan tujuh-segmen yang menunjukkan susunan segmen menngunakan sambungan 'common anode'. Tunjukkan setiap langkah dengan jelas untuk menghasilkan ungkapan dan reka bentuk yang dikehendaki.] Xs X6 X7 DECODER Figure 1(a) [Rajah 1(a)] a b с d e f g a 80123456789 Figure 1(c) [Rajah 1(c)] g Figure 1 (b) [Rajah 1(b)] b с DP