Answer the following based on the image below; What does this code do with R2 and R3 to compute R4? Answer with one simple line of valid C code of the form: R4 = exp;, where exp is a simple C expression using the the variables R2 and R3. exp must not include C statements like loops or conditionals. PC2-InstructionMemoryReadAddress+[15:12][11:8]Inst 16 [7:4][3:0]1016ControlUnitRead Addr 1Write EnableRead Addr 2MemWrite AddrReg WriteWrite Data4Register FileReadData 1ReadData 2Shift left by 11616Sign extend 16HW microarchitecture datapath01+BranchALUControlALUzero flag1601Mem StoreAddressWrite EnableData MemoryWriteDataReadData0 1 Execute this code,assuming R2 holds 5 and R3 holds 3.Indicate the final register values when thecode reaches HALT.0: AND R2, R2, R42:AND R3, R3, R5BEQ R5, RO, 3SUB R5, R1, R5ADD R4, R4, R4JMP 2HALT # Stops execution.R3:4:6:8:A:C:R2:R4:R5:

To compute R4 using R2 and R3:R4 = R2 * R3;

Answered: Answer the following based on the image…

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Answer the following based on the image below; What does this code do with R2 and R3 to compute R4? Answer with one simple line of valid C code of the form: R4 = exp;, where exp is a simple C expression using the the variables R2 and R3. exp must not include C statements like loops or conditionals.

PC
2-
Instruction
Memory
Read
Address
+
[15:12]
[11:8]
Inst 16 [7:4]
[3:0]
1
0
16
Control
Unit
Read Addr 1
Write Enable
Read Addr 2
Mem
Write Addr
Reg Write
Write Data
4
Register File
Read
Data 1
Read
Data 2
Shift left by 1
16
16
Sign extend 16
HW microarchitecture datapath
0
1
+
Branch
ALU
Control
ALU
zero flag
16
0
1
Mem Store
Address
Write Enable
Data Memory
Write
Data
Read
Data
0 1

Execute this code,
assuming R2 holds 5 and R3 holds 3.
Indicate the final register values when the
code reaches HALT.
0: AND R2, R2, R4
2:
AND R3, R3, R5
BEQ R5, RO, 3
SUB R5, R1, R5
ADD R4, R4, R4
JMP 2
HALT # Stops execution.
R3:
4:
6:
8:
A:
C:
R2:
R4:
R5:

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